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preliminary information AMD-645 peripheral bus controller data sheet tm
? 1997 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. ("amd") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life support devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products except as provided in amds terms and conditions of sale for such product. preliminary information trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. amd-640, AMD-645, k86, amd-k5, and amd-k6 are trademarks of advanced micro devices, inc. mmx is a trademark of the intel corporation. microsoft and windows are registered trademarks, and windows nt is a trademark of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
table of contents iii 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information contents 1 features 1-1 1.1 enhanced ide controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 universal serial bus controller . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 plug-n-play support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.4 sophisticated power management . . . . . . . . . . . . . . . . . . . . . 1-2 1.5 pc97-compliant pci-to-isa bridge . . . . . . . . . . . . . . . . . . . . 1-3 2overview 2-1 2.1 pci-to-isa bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 pci bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 pci bus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 isa controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 eide controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4 universal serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 3 ordering information 3-1 4 signal descriptions 4-1 4.1 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 isa bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 ultra dma-33 enhanced ide interface . . . . . . . . . . . . . . . 4-10 4.4 xd bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.5 plug-n-play support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.6 universal serial bus interface . . . . . . . . . . . . . . . . . . . . . . . 4-15
iv table of contents AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 4.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.8 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.9 internal real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.10 keyboard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.11 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.12 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 5 functional operations 5-1 5.1 pci bus-initiated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 bus cycle decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 pci bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.2 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.3 i/o read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.4 memory read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.5 configuration read/write . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.2.6 memory read multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.2.7 dual address line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.2.8 memory read line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.2.9 memory write invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3 pci bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.1 back-to-back cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2 subtractive decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.3 isa bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.4 isa bus-initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.1 dma-initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.2 isa bus master initiated cycles . . . . . . . . . . . . . . . . . . . . . 5-20 5.5 pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.6 i/o and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.6.1 i/o mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6.3 system rom memory mapping . . . . . . . . . . . . . . . . . . . . . 5-26
table of contents v 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.7 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.8 direct memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.8.1 dma controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.8.2 dma controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.8.3 middle address bit latches . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.8.4 page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.8.5 dma address generation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.8.6 type f dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.8.7 dma channel mapping registers . . . . . . . . . . . . . . . . . . . 5-37 5.8.8 ready control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.8.9 external cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5.9 distributed dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.10 ultra dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.10.1 ultra dma read burst command . . . . . . . . . . . . . . . . . . . 5-41 5.10.2 ultra dma write burst command . . . . . . . . . . . . . . . . . . . 5-43 5.10.3 slave dma channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5.10.4 dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 5.10.5 dma software commands . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.10.6 dma addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.10.7 pci slave dma configuration registers . . . . . . . . . . . . . . 5-50 5.11 isa bus refresh cycle types . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5.12 fast ide/eide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5.12.1 ide drive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5.12.2 pci cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.12.3 dma bus mastering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 5.12.4 ide channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.12.5 ide configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5.13 power management support . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 5.13.1 power management subsystem . . . . . . . . . . . . . . . . . . . . . 5-58 5.13.2 power plane management . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 5.13.3 power management events . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 5.13.4 legacy management timers . . . . . . . . . . . . . . . . . . . . . . . . 5-64 5.13.5 system primary and secondary events . . . . . . . . . . . . . . . 5-65 5.13.6 peripheral events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
vi table of contents AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 6 initialization 6-1 6.1 legacy i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 pci function 0 registerspci-to-isa bridge . . . . . . . . . . . 6-5 6.3 pci function 1 registerside control . . . . . . . . . . . . . . . . 6-8 6.4 pci function 2 registersusb controller . . . . . . . . . . . . 6-10 6.5 pci function 3 registerspower management . . . . . . . . . 6-12 6.5.1 power management configuration space registers . . . . 6-12 6.5.2 power management i/o space registers . . . . . . . . . . . . . . 6-13 7 registers 7-1 7.1 pci mechanism #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 legacy i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.1 keyboard controller registers . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.2 dma controller i/o registers . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2.3 interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.4 interrupt controller shadow registers . . . . . . . . . . . . . . . 7-10 7.2.5 timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.6 cmos/rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.3 function 0 registers (pci-isa bridge) . . . . . . . . . . . . . . . . 7-15 7.3.1 function 0 pci configuration space header . . . . . . . . . . 7-15 7.3.2 isa bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.3 plug-n-play control registers . . . . . . . . . . . . . . . . . . . . . . 7-24 7.3.4 distributed dma control . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7.4 function 1 registers (enhanced ide controller) . . . . . . . 7-29 7.4.1 function 1 pci configuration space header . . . . . . . . . . 7-29 7.4.2 ide controller-specific configuration registers . . . . . . . 7-36 7.4.3 ide i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 7.5 function 2 registers (usb controller) . . . . . . . . . . . . . . . . 7-44 7.5.1 function 2 pci configuration space header . . . . . . . . . . 7-45 7.5.2 usb-specific configuration registers . . . . . . . . . . . . . . . . 7-48 7.5.3 usb i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
table of contents vii 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7.6 function 3 registers (power management) . . . . . . . . . . . . 7-51 7.6.1 function 3 pci configuration space header . . . . . . . . . . 7-51 7.6.2 power management-specific configuration registers . . . 7-54 7.6.3 power management i/o space registers . . . . . . . . . . . . . . 7-58 8 electrical data 8-1 8.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 9 switching characteristics 9-1 9.1 pclk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 valid delay, float, setup, and hold timings . . . . . . . . . . . . 9-6 9.3 pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.4 isa interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5 dma interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.6 x-bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 9.7 eide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.8 ultra dma-33 ide bus interface timing . . . . . . . . . . . . . . 9-30 10 i b i s models 10-1 10.1 i/o buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 i/o model application note . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 10-3 10.4 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
viii table of contents AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 11 pin designations 11-1 11.1 pin designation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 12 package specifications 12-1
list of figures ix 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information list of figures figure 1-1. amd-640 chipset system block diagram . . . . . . . . . . . . . . . 1-4 figure 2-1. AMD-645 peripheral bus controller block diagram . . . . . . 2-8 figure 5-1. i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-2. i/o cycle 16-bit to 8-bit conversion . . . . . . . . . . . . . . . . . . . 5-5 figure 5-3. non-posted pci-to-isa access . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-4. posted pci-to-memory write . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-5. isa bus memory access cycle . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-6. isa bus memory cycle: 16-bit to 8-bit conversion . . . . . . . 5-9 figure 5-7. memory cycle 32-bit to 8-bit conversion . . . . . . . . . . . . . . 5-10 figure 5-8. memory cycle 32-bit to 16-bit conversion . . . . . . . . . . . . . 5-11 figure 5-9. rom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 figure 5-10. rom cycle 32-bit to 8-bit conversion . . . . . . . . . . . . . . . . 5-13 figure 5-11. configuration read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-12. configuration write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-13. subtractive decode timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 figure 5-14. dma transfer cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-15. isa bus master arbitration timing . . . . . . . . . . . . . . . . . . 5-21 figure 5-16. isa bus master-to-pci memory (memory read) . . . . . . . . 5-22 figure 5-17. isa bus master-to-pci memory (memory write). . . . . . . . 5-22 figure 5-18. type f dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 figure 5-19. dma ready timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 figure 5-20. ultra dma-33 ide read burst. . . . . . . . . . . . . . . . . . . . . . . 5-41 figure 5-21. pausing a dma burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 figure 5-22. drive terminating a dma read burst . . . . . . . . . . . . . . . . 5-42 figure 5-23. host terminating dma burst during read command . . . 5-43 figure 5-24. ultra dma-33 ide write burst . . . . . . . . . . . . . . . . . . . . . . 5-44 figure 5-25. drive terminating dma burst during write command. . 5-45 figure 5-26. host terminating dma burst during write command . . 5-45 figure 5-27. pio cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 figure 5-28. ide multiword dma cycle . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 figure 7-1. strap option circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 figure 9-1. pclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 figure 9-2. setup, hold, and valid delay timing diagram . . . . . . . . . . 9-6 figure 9-3. isa master interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 figure 9-4. isa 8-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . 9-11 figure 9-5. isa 16-bit slave interface timing . . . . . . . . . . . . . . . . . . . . 9-13 figure 9-6. isa master-to-pci access timing . . . . . . . . . . . . . . . . . . . . 9-15 figure 9-7. other isa master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
x list of figures AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 9-8. dma read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 figure 9-9. dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 figure 9-10. type f dma interface timing . . . . . . . . . . . . . . . . . . . . . . . 9-23 figure 9-11. x-bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 figure 9-12. eide pio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 figure 9-13. eide dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 figure 11-1. AMD-645 peripheral bus controller pin diagram . . . . . . . 11-4 figure 12-1. 208-pin plastic quad flat pack outline drawing . . . . . . . 12-2
list of tables xi 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information list of tables table 3-1. valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 table 4-1. connecting pirq lines to pci int lines . . . . . . . . . . . . . . . . 4-3 table 5-1. pci bus command encoding and types . . . . . . . . . . . . . . . . . 5-2 table 5-2. isa byte and word accesses. . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 5-3. i/o fixed address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 table 5-4. memory address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 table 5-5. rom decode control register . . . . . . . . . . . . . . . . . . . . . . . . 5-27 table 5-6. isa bus clock select bit programming . . . . . . . . . . . . . . . . . 5-28 table 5-7. ports 00hC0fh master dma controller . . . . . . . . . . . . . . . . . 5-30 table 5-8. ports 80hC8fh dma page register access . . . . . . . . . . . . . . 5-32 table 5-9. dma addressing for isa bus accesses (dma/slot bus) . . . 5-34 table 5-10. dma addressing for isa bus accesses (dma/pci ad bus) 5-35 table 5-11. type f dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 table 5-12. ultra dma interface signals . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 table 5-13. programming model for single slave dma channel . . . . . . 5-46 table 5-14. dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 table 5-15. ide register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 table 5-16. pci cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 table 5-17. sci/smi/resume control for pm events . . . . . . . . . . . . . . . . 5-63 table 5-18. suspend resume events and conditions. . . . . . . . . . . . . . . . 5-63 table 5-19. pri_act_sts and pri_act_en register bits . . . . . . . . . . 5-65 table 6-1. master dma controller registers . . . . . . . . . . . . . . . . . . . . . . 6-1 table 6-2. master interrupt controller registers. . . . . . . . . . . . . . . . . . . 6-2 table 6-3. timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-4. keyboard controller registers . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-5. cmos/rtc/nni registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-6. dma page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 table 6-7. system control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 table 6-8. slave interrupt controller registers . . . . . . . . . . . . . . . . . . . . 6-3 table 6-9. slave dma controller registers . . . . . . . . . . . . . . . . . . . . . . . 6-4 table 6-10. configuration space pci-to-isa header registers . . . . . . . . 6-5 table 6-11. isa bus control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 table 6-12. plug-n-play control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 table 6-13. distributed dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 table 6-14. configuration space ide header registers . . . . . . . . . . . . . . 6-8 table 6-15. configuration space ide registers . . . . . . . . . . . . . . . . . . . . . 6-9 table 6-16. ide controller i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 table 6-17. configuration space usb header registers . . . . . . . . . . . . . 6-10 table 6-18. configuration space usb registers. . . . . . . . . . . . . . . . . . . . 6-11 table 6-19. usb controller i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 table 6-20. configuration space power management header registers 6-12 table 6-21. configuration space power management registers . . . . . . 6-13 table 6-22. basic power management control/status registers. . . . . . . 6-13
xii list of tables AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 6-23. processor power management registers. . . . . . . . . . . . . . . . 6-14 table 6-24. general purpose power management registers. . . . . . . . . . 6-14 table 6-25. generic power management registers . . . . . . . . . . . . . . . . . 6-14 table 6-26. general purpose i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 table 7-1. keyboard controller command codes . . . . . . . . . . . . . . . . . . 7-4 table 7-2. traditional port pin definition. . . . . . . . . . . . . . . . . . . . . . . . . 7-6 table 7-3. ports 00hC0fh master dma controller . . . . . . . . . . . . . . . . . . 7-8 table 7-4. ports c0hCdfh slave dma controller. . . . . . . . . . . . . . . . . . . 7-9 table 7-5. ports 80hC8fh dma page registers. . . . . . . . . . . . . . . . . . . . . 7-9 table 7-6. ports 20hC21h master interrupt controller registers . . . . . 7-10 table 7-7. ports a0hCa1h slave interrupt controller registers. . . . . . 7-10 table 7-8. ports 40hC43h timer/counter registers . . . . . . . . . . . . . . . . 7-12 table 7-9. cmos register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 table 7-10. compatibility mode vs. native pci mode . . . . . . . . . . . . . . . 7-31 table 7-11. fifo distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 table 8-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 table 8-2. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 table 8-3. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 8-4. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 table 8-5. typical and maximum power dissipation . . . . . . . . . . . . . . . . 8-4 table 9-1. clk switching characteristics for 33-mhz pci bus . . . . . . . 9-3 table 9-2. usbclk switching characteristics for 12-mhz usb bus . . . 9-4 table 9-3. usbclk switching characteristics for 1.5-mhz usb bus. . . 9-4 table 9-4. bclk switching characteristics for 8-mhz bus . . . . . . . . . . . 9-5 table 9-5. osc switching characteristics for 14.3182-mhz bus . . . . . . . 9-5 table 9-6. pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 table 9-7. isa master interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 table 9-8. isa 8-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . . 9-10 table 9-9. isa 16-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . 9-12 table 9-10. isa master-to-pci access timing . . . . . . . . . . . . . . . . . . . . . . 9-14 table 9-11. other isa master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 table 9-12. dma read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 table 9-13. dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 table 9-14. type f dma interface timing . . . . . . . . . . . . . . . . . . . . . . . . 9-22 table 9-15. x-bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 table 9-16. eide pio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 table 9-17. eide dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 table 9-18. ultradma-33 ide bus interface timing . . . . . . . . . . . . . . . . 9-30 table 11-1. functional grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
features 1-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 1features the amd-640? chipset is a highly integrated system solution designed to deliver superior performance for the amd-k5? processor, amd-k6? mmx? enhanced processor, and other socket 7-compatible processors. the amd-640 chipset consists of the amd-640 system controller in a 328-pin bga package and the AMD-645? peripheral bus controller in a 208-pin pqfp package. the AMD-645 peripheral bus controller features an integrated isa bus controller, enhanced master mode pci ide controller with ultra dma-33 support, usb controller, keyboard/mouse controller, and real-time clock. this document describes the features and operation of the AMD-645 peripheral bus controller. for a description of the amd-640 system controller, see the amd-640 system controller data sheet , order# 21090. key features of the AMD-645 peripheral bus controller are provided in this section. 1.1 enhanced ide controller n enhanced master mode pci ide controller with ultra dma- 33 support n dual channel master mode pci supporting four enhanced ide devices n transfer rate up to 33 mbytes per second to cover pio mode 4 and multi-word dma mode 2 drivers, and ultra dma- 33/ata-33 interface n sixteen levels (doublewords) of prefetch and write buffers n interlaced commands between the two channels n bus master programming interface for sff-8038i, rev. 1.0 and microsoft ? windows ? 95 compliance n full scatter-gather capability n supports atapi-compliant devices n supports pci native and ata compatibility modes n complete software driver support
1-2 features AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 1.2 universal serial bus controller n usb v. 1.0 and intel universal hci v. 1.1-compatible n eighteen-level (doubleword) data fifos n root hub and two function ports with built-in physical layer transceivers 1.3 plug-n-play support n pci interrupts steerable to any interrupt channel n microsoft windows 95 and plug-n-play bios compliant 1.4 sophisticated power management n supports both acpi (advanced configuration and power interface) and legacy (apm) power management n acpi v.0.9 compliant n apm v.1.2 compliant n supports soft-off and power-on suspend with hardware automatic wakeup n one idle timer, one peripheral timer, and one general purpose timer, plus 24- or 32-bit apci-compliant timer n dedicated input pin for external modem ring indicator for system wakeup n normal, doze, sleep, suspend, and conserve modes n system event monitoring with two event classes n five multipurpose i/o pins plus support for up to 16 general purpose input ports and 16 output ports n primary and secondary interrupt differentiation for individual channels n clock throttling control n multiple internal and external smi# sources for flexible power management
features 1-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 1.5 pc97-compliant pci-to-isa bridge n dual cascaded at-compatible 8259 interrupt controllers n at-compatible 8255 programmable interval timer n dual at-compatible 8237 dma controllers n distributed dma support for isa legacy dma across the pci bus n integrated keyboard controller with ps/2 mouse support n integrated real-time clock with extended 256-byte cmos ram n pci v. 2.1-compliant interface n eight double-word line buffer between pci and isa bus n supports type f dma transfers n fast reset and gate a20 operation n edge-triggered or level-sensitive interrupts n flash, 2-mbyte eprom, and combined bios support n programmable isa bus clock n supports external ioapic interface with symmetrical multiprocessor configurations
1-4 features AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 1-1. amd-640 chipset system block diagram ethernet southbridge l2 cache dram pci bus isa usb system management lan scsi 64-bit 64-bit host bus 32-bit 16-bit dram memory bus serr# preq# pgnt# eide system controller x-bus 8-bit bios amd-k6 processor amd-640 system controller AMD-645 peripheral bus controller
overview 2-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 2 overview the AMD-645 peripheral bus controller is responsible for converting between pci and isa bus cycles. the AMD-645 peripheral bus controller pci-to-isa bridge contains eight double-word line buffers and supports type f dma transfers and delay transactions to streamline pci bus operation and comply with pci specification version 2.1. the AMD-645 peripheral bus controller also integrates many at-compatible and system control functions, including a keyboard controller with ps/2 mouse support, real-time clock with extended 256-byte cmos ram, master mode eide controller with full scatter and gather capability, and a usb interface with root hub and two function ports with built-in physical layer transceiver. 2.1 pci-to-isa bridge the AMD-645 peripheral bus controller offers both a pci- compatible bus interface and an isa-compatible interface. these interfaces, which are fully compliant with the pci 2.1 specification, control pci/isa bus communication. two main blocks, the pci bus master and slave blocks, make up the pci interface control. to become pci bus master, the AMD-645 peripheral bus controller must arbitrate for control of the bus with the amd-640 system controller. once bus ownership has been granted, the AMD-645 peripheral bus controller assumes pci bus master responsibility. the AMD-645 peripheral bus controller is in slave mode whenever it does not own the pci bus.
2-2 overview AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 2.1.1 pci bus master mode the AMD-645 peripheral bus controller arbitrates for bus ownership when an isa bus resource requests a dma- controlled transfer between memory and an i/o device, or when an isa bus master requests bus ownership for data transfers. in both dma and isa master mode, the data transfer takes place either between two isa bus resources or between an isa and a pci bus resource. to determine the destination of the bus master request, the AMD-645 peripheral bus controller can sample an active devsel# input, which indicates that a particular target on the pci bus is responding to the current request. the destination can also be determined by a positive decoding of the master- driven address. a third alternative for determining the destination is subtractive decode. if the destination is not identified by either positive address decoding or an active devsel# input, the AMD-645 peripheral bus controller assumes the access is occurring only between two isa bus resources. the AMD-645 peripheral bus controller pci interface translates all non-positive decoded isa master requests to the pci bus. in situations in which the request is forwarded to the pci bus, the AMD-645 peripheral bus controller ensures isa and pci bus synchronization by controlling the isa-based iochrdy signal. if an active devsel# response is not received within the specified time, the AMD-645 peripheral bus controller master interface assumes the requested cycle was between isa resources and executes a pci master abort cycle. in the event the devsel# signal is sampled active within the specified time, the AMD-645 peripheral bus controller master interface executes a data transfer between the isa and pci buses. 2.1.2 pci bus slave mode the AMD-645 peripheral bus controller stays in pci slave mode when it does not own the bus. the slave interface responds to any request from a pci resource by asserting devsel# if it has positively decoded the current address as a destination for either the isa bus or for on-chip i/o.
overview 2-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information when the current address is not positively decoded, the AMD-645 peripheral bus controller target interface is de- selected by an active devsel# input driven by another pci resource. if no active devsel# signal is received within a specified time, the AMD-645 peripheral bus controller acts as the subtractive decode resource by claiming all otherwise unclaimed pci bus requests and directing the request to the isa bus. to ensure correct data synchronization between the two buses on pci-to-isa write cycles, the isa command sequence begins only after the current pci master has indicated valid data on the bus by asserting irdy#. the AMD-645 peripheral bus controller responds to requests destined for the isa bus or on-chip i/o by executing a single data transfer and signalling a target disconnect. if the AMD-645 peripheral bus controller samples an active devsel# input within a specified time, it is de-selected, allowing the transfer to take place between the two pci resources. the AMD-645 peripheral bus controller is capable of posting pci-to-isa memory write cycles. when posting is enabled, the pci request is acknowledged immediately and the write data is latched to allow the isa cycle to proceed independently from the pci transaction. 2.2 isa controller the integrated isa system address latches and control logic allow the AMD-645 peripheral bus controller user to design an extremely cost-effective system. in addition, the AMD-645 peripheral bus controller contains the decode logic to select an external keyboard controller. this keyboard controller can be programmed for attachment on either the xd or sd bus. the AMD-645 peripheral bus controller controls accesses to 8- bit bios rom and to 8-bit or 16-bit isa bus rom. the bios rom must be 8 bits and is accessed via an external xd bus. all other rom is accessed as either 8-bit or 16-bit rom residing
2-4 overview AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information on the isa sd bus, either on-board or off-board via the slots. accesses in the c0000hCcffffh and e0000hCeffffh ranges are optionally definable as on-board system rom or off-board memory via the rom relocation register. a special mode is supported for erasing and programming flash memories in areas where such devices are used as the bios roms. the 82c37a-compatible dma controllers control data transfers between an i/o channel and on-board or off-board memory. the dma controllers can transfer data over a 24-bit (16- mbyte) address range. internal latches latch the middle address bits output by the 8237a megacells. a memory mapper generates the upper address bits. as specified by the industry standard, distributed dma offers support for seven dma channels. the distributed dma logic remaps i/o cycles from the distributed i/o target locations to the applicable dma controller. when this remapping is enabled, accesses to the legacy dma i/o addresses are disabled and isa cycles are generated instead. dma requests from the isa bus that address pci memory cause pci master requests and cycles to be generated by the AMD-645 peripheral bus controller. the AMD-645 peripheral bus controller generates synchronous isa bus timing and synchronous ide interface timing from the 33-mhz pci bus clock. the AMD-645 peripheral bus controller performs all the data steering functions between the isa bus and the pci bus. pci bus data accesses that are wider than those supported by the targeted isa bus device are automatically split into two, three, or four isa cycles. when pci bus reads are split into several isa bus reads, the data returned by the isa devices is assembled by latches before being returned to the pci bus. the AMD-645 peripheral bus controller also performs low-to- high and high-to-low byte swaps on the 16-bit sd bus. as a pci slave, the AMD-645 peripheral bus controller is capable of expanding pci accesses with non-contiguous byte enables into the appropriate discrete isa cycles. the AMD-645 peripheral bus controller functions are programmable via a set of internal device-specific
overview 2-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information configuration registers. the state of various interface pins on reset is used to determine the default configuration. 2.3 eide controller the AMD-645 peripheral bus controllers enhanced ide interface provides a variety of features to optimize system performance. a 16-doubleword write fifo and look-ahead read buffer supports 32-bit pci data transfers. the ide-pci interface operates at pci speed and allows concurrent ide and pci operations to maximize system performance. logically, the ide drive interface can be viewed as being composed of six controller blocks. cpu command processor the cpu command processor receives input commands from the cpu, fifo full/fifo empty signals from the write-fifo, and read-ahead full signals from the read-ahead buffer. i/o processor the i/o processor is the ide control signal block, containing all of the ide bus control logic. it receives inputs from the ide bus, command processor, and write fifo. the i/o processor issues the ior#/iow# signals to the ide bus, based on programmed address setup time, ior#/iow# precharge time, and ior#/iow# active duration. it also translates 16-bit cycles to two 8-bit cycles when necessary. write buffer the write buffer takes 32-bit cpu data and converts it to the proper 16-bit or 8-bit data format. read-ahead/posted- write fifo this block functions as a read-ahead buffer during read accesses from i/o address 1f0h. during writes, this block stores 16-bit data in the 16-doubleword fifo and passes control to the i/o processor or dma state machine. its direction is determined by commands and register programming. ide arbiter the arbiter arbitrates between ide channels and multiplexes the ide data bus, ide address, and ide chip selects. dma state machine the dma bus mastering state machine controls iow# and ior# pulses for each ide channel during dma accesses.
2-6 overview AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information the AMD-645 peripheral bus controllers enhanced ide controller provides a data path and control interface to standard ide drives. the block is fully compatible with the ansi ata specifications for ide hard disk operation. the bus mastering ide interface supports transfer rates up to and beyond mode 4-programmed i/o and mode 2 dma. two channels are supported with the ability to connect to both with no external logic. data is transferred over a shared 16-bit ide data bus. the AMD-645 peripheral bus controller contains two ide interfaces. channel 0 is the primary interface, with target i/o addresses at 1f0hC1f7h and 3f6h. its irq pin is mapped to irq14. channel 1 is the secondary ide interface, with target i/o addresses at 170hC177h and 376h. its irq pin is mapped to irq15. unless otherwise noted, discussions in this document referring to channel 0 resources apply equally to the respective channel 1 resources. the master mode registers for both channels are contained in a single i/o block located at the i/o address specified by the contents of the bus master control registers base address register located at function 1, offset 23hC20h. the first 8 bytes of the 16-byte block are associated with channel 0, and the second 8 bytes with channel 1. independent configuration registers exist in pci configuration space for each channel. 2.4 universal serial bus the AMD-645 peripheral bus controller usb host controller interface is fully compatible with both the usb specification v.1.0 and the intel universal hci specification v.1.1. there are two sets of software-accessible registers, the pci configuration registers and the usb i/o registers. the interface supports eighteen levels (doublewords) of data fifos, and a root hub and two function ports with built-in physical layer transceivers. the usb controller allows hot plug-n-play and isochronous peripherals to be inserted into the system with universal driver support.
overview 2-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information in addition, the AMD-645 peripheral bus controller offers legacy (x-bus) keyboard and ps/2 mouse support. 2.5 power management the AMD-645 peripheral bus controller supports advanced configuration and power interface (acpi) as well as legacy advanced power management (apm). it complies with both acpi specification v.0.9 and apm specification v.1.2. in addition, AMD-645 peripheral bus controller power management is compatible with pc97 and onnow. the real-time clock with 256-byte extended cmos includes a data alarm and other enhancements for compatibility with the acpi standard. two types of sleep states are provided, soft-off and power-on suspend, along with hardware automatic wake- up. additional power management features includes event monitoring, cpu clock throttling, hardware and software- based event handling, general purpose io, and external smi.
2-8 overview AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 2-1. AMD-645 peripheral bus controller block diagram cpurst ferr# ignne# intr init nmi smi# stpclk# bclk osc pcirst# pwrgd rstdrv ad31-ad0 devsel# frame# irdy# pirq[d:a]# c/be[3:0]# par preq# pgnt# serr# stop# pclk trdy# idsel rtcx1/irq8# rtcx2/rtccs# vbat processor pci bus real-time reset & plug-n-play mirq0#/apiccs# mirq1/keylock mirq2/master# xd interface romcs#/kbcs# xdir xd[7:0] universal usbclock usbdata0C usbdata0+ usbdata1C usbdata1+ isa bus aen bale iocs16# ior# iow# irq15,14,11C9,7C3 la23/dcs3b# la22/dcs1b# la21/dcs3a# la20/dcs1a# la[19:17]/da[2:0] memcs16# memr# memw# refresh# sa16 sbhe# spkr tc drq[7:5], drq[3:0] iochck# iochrdy sa[15:0]/dd[15:0] sd[15:8] smemr# smemw# enhanced ddacka# ddackb# ddrqa ddrqb diora#/hdmardya#/hstrobea diorb#/hdmardyb#/hstrobeb diowb#/stopb drdya#/ddmardya#/dstrobea drdyb#/ddmardyb#/dstrobeb soe# diowa#/stopa keyboard a20m# kbck/ka20g keylock msck/irq1 msdt/irq12 kbdt/kbrc# dack[7:5]#, dack[3:0]# pwrbtn pwron clock interface clock serial interface control ide interface interface ri# power management power management gpio1/extsmi1# gpio2/extsmi2# gpio4/extsmi4#/gpo_we gpio3/extsmi3#/gpi_re# gpio0/extsmi0# 4-dword write buffer 4-dword prefetch buffer
ordering information 3-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 3 ordering information amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. family/core table 3-1. valid combinations opn package type operating voltage case temperature AMD-645 208-pin pqfp 4.75 vC5.25 v 70 c notes: valid combinations are configurations that are or will be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. AMD-645
3-2 ordering information AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information
signal descriptions 4-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 4 signal descriptions 4.1 pci bus interface ad[31:0] pci address/data bus bidirectional ad[31:0] are the standard pci address and data lines. they contain a physical address during the first clock of a pci transaction, and data during subsequent clocks. the address is driven when frame# is asserted, and data is driven or received in subsequent cycles. when the AMD-645 peripheral bus controller is pci master, these lines are outputs during the address and write data phases of a transaction, and inputs during the read data phase. when the AMD-645 peripheral bus controller is pci slave, these lines are inputs during the address and write data phases of a transaction, and outputs during the read data phase. c3/be[3:0]# pci command / byte enable bidirectional during the first clock of a pci transaction, when frame# is asserted, these lines contain the pci bus command (c[3:0]). on subsequent clocks, these lines contain pci byte enables (be[3:0]#) corresponding to supplied or requested data. be[3:0]# are outputs when the AMD-645 peripheral bus controller is the pci bus master. they are inputs when it is the slave. devsel# pci bus device select bidirectional when the AMD-645 peripheral bus controller is pci bus master, devsel# is an input that determines whether a slave has responded to the current address. if devsel# is sampled inactive in the fourth pclk cycle after frame# is asserted, the AMD-645 peripheral bus controller aborts the pci bus cycle.
4-2 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information when the AMD-645 peripheral bus controller is not pci bus master it defaults to target mode, and devsel# is an output indicating that it claims a pci transaction through either positive or subtractive decoding. in a positive decode, the AMD-645 peripheral bus controller asserts devsel# one pclk cycle after frame# is sampled active and holds it low through the end of the transaction. in a subtractive decode, devsel# is driven low three pclk cycles after frame# is asserted. positive and negative decoding are explained in section 5.1 on page 5-1. frame# pci bus cycle frame bidirectional the assertion of frame# indicates the address phase of a pci transfer, while its negation indicates that one more data transfer is desired by the cycle initiator. while frame# is asserted, data transactions can continue. when frame# is deasserted, data transactions are in the final phase. when the AMD-645 peripheral bus controller is pci bus master, frame# is driven active for one clock cycle to start the current bus cycle. when the AMD-645 peripheral bus controller is the slave, frame# is an input indicating the beginning and duration of the current bus cycle. idsel pci initialization device select input idsel is used as a chip select during configuration read and write cycles. irdy# pci bus initiator ready bidirectional irdy# is asserted by a pci initiator from the first clock cycle after frame# to the last clock of the transaction to indicate it is ready for data transfer. when the AMD-645 peripheral bus controller is pci master, irdy# is an output that indicates the ability of the chip to complete the current data phase of the transaction. when the AMD-645 peripheral bus controller is pci slave, a read cycle cannot end and the write cycle cannot start until the irdy# input is sampled active.
signal descriptions 4-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information par pci bus parity bidirectional this signal provides even parity for ad[31:0] and c/be[3:0]#. when the AMD-645 peripheral bus controller is pci bus master, it drives par one pclk after the address and write data phases. when the AMD-645 peripheral bus controller is pci slave, it samples the par input one clock after a read is completed. pcirst# pci reset output pcirst# is an active low reset signal for the pci bus. the AMD-645 peripheral bus controller can assert reset during power-up. a pci reset can be forced during normal operation by setting configuration register function 0, offset 47h, bit 0. pclk pci bus clock input pclk provides timing for all transactions on the pci bus. it runs at half the cpu frequency, up to 33 mhz. pclk can also be divided down to generate the isa bus clock. pgnt# pci grant input the amd-640 system controller drives pgnt# to grant pci bus access to the AMD-645 peripheral bus controller. pirq[d:a]# pci interrupt requests input these pins are typically connected to the pci bus int lines as shown in table 4-1. preq# pci request output the AMD-645 peripheral bus controller asserts preq# to request control of the pci bus. table 4-1. connecting pirq lines to pci int lines pirqa# pirqb# pirqc# pirqd# pci slot 1 inta# intb# intc# intd# pci slot 2 intb# intc# intd# inta# pci slot 3 intc# intd# inta# intb# pci slot 4 intd# inta# intb# intc#
4-4 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information serr# system error input any pci device that detects a system error condition can alert the system by asserting serr# for one pci clock. the AMD-645 peripheral bus controller can be programmed to generate an nmi to the cpu if it samples serr# active. stop# stop bidirectional a pci target asserts stop# to request that the master stop the current transaction. when the AMD-645 peripheral bus controller is pci master, stop# is an input that causes the AMD-645 peripheral bus controller to terminate the transfer and abort or retry it depending on the state of devsel# and trdy#. when the AMD-645 peripheral bus controller is pci slave, it asserts stop# and trdy# simultaneously to indicate a target disconnect following the data transfer or burst. it does not assert stop# if the transfer is a single, non-bursted transfer. trdy# pci target ready bidirectional a pci target asserts trdy# when it is ready for data transfer. when the AMD-645 peripheral bus controller is the pci master, trdy# is an input that indicates the ability of the target device to complete the data phase of the transaction. once a pci bus transaction is initiated, the AMD-645 peripheral bus controller inserts wait cycles until trdy# is sampled active. as the pci slave, the AMD-645 peripheral bus controller asserts trdy# to indicate it has sampled the data from the pci address/data bus during a write phase, or presented valid data on the bus during a read phase. 4.2 isa bus interface aen address enable output aen is asserted during dma transfer cycles to the i/o resources on the bus to prevent i/o slaves from misinterpreting dma cycles as valid i/o cycles. it is asserted only when the dma controller is the bus owner.
signal descriptions 4-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bale bus address latch enable output bale is asserted for a bus clock at the beginning of any bus cycle initiated by a pci master. it is asserted by the AMD-645 peripheral bus controller to indicate that the address signal lines (sa[19:0], la[23:17], and sbhe#) are valid. bclk bus clock output bclk is the isa bus clock. dack[7:5]#, cack[3:0]# dma acknowledge output these lines indicate that the corresponding request for dma service has been accomplished. drq[7:5], drq[3:0] dma request input these asynchronous dma request lines are used by external devices to request services from the AMD-645 peripheral bus controller dma controller. drq[3:0] are used for transfers between 8-bit i/o adapters and system memory. drq[7:5]are used for transfers between 16-bit i/o adapters and system memory. drq4 is not available externally. iochck# i/o channel check input iochck# is asserted by a device or memory on the isa bus to indicate that a parity error or other uncorrectable error has occurred. if i/o checking is enabled, the AMD-645 peripheral bus controller generates an nmi to the processor when it samples iochck# asserted. iochrdy i/o channel ready input devices on the isa bus negate iochrdy to indicate that additional time is required to complete the cycle. the cycle can be generated by the cpu, dma controllers, or refresh controller. the AMD-645 peripheral bus controller responds by inserting wait states to add more time to the cycle. the default number of wait states for cycles initiated by the cpu is as follows: n 8-bit peripherals 4 wait states n 16-bit peripherals 1 wait state
4-6 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information n rom cycles 3 wait states one dma wait state is inserted as the default for all dma cycles. any peripheral that cannot present read data or strobe in write data in this amount of time must assert iochrdy to extend these cycles. the AMD-645 peripheral bus controller always drives iochrdy low in either dma or master mode to allow for pci bus latency. iocs16# 16-bit i/o chip select input iocs16# is driven by i/o devices on the isa bus to indicate that they support 16-bit i/o bus cycles. the AMD-645 peripheral bus controller samples iocs16# to determine when a cpu access requires a 16-bit to 8-bit conversion. it also performs a conversion if it requests a 16-bit i/o cycle and samples iocs16# high. in a conversion, the AMD-645 peripheral bus controller inserts a command delay of one bus cycle and the cycle becomes four wait states long. if iocs16# is sampled low, the AMD-645 peripheral bus controller performs an i/o access in one wait state, inserting one command delay. ior# i/o read bidirectional ior# is the command to an isa i/o slave device indicating the slave can drive data onto the isa data bus. ior# is an input when the AMD-645 peripheral bus controller is bus master and an output at all other times. when the AMD-645 peripheral bus controller is a pci slave, ior is driven by the internal isa bus controller. during dma transfers, ior# is driven by the dma controller. it is inactive during a refresh cycle. iow# i/o write bidirectional iow# is the command to an isa i/o slave device indicating the slave can latch data from the isa data bus.
signal descriptions 4-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information iow# is an input when the AMD-645 peripheral bus controller is bus master and an output at all other times. when the AMD-645 peripheral bus controller is a pci slave, iow# is driven by the internal isa bus controller. during dma transfers, iow# is driven by the dma controller. it is inactive during a refresh cycle. irq15, irq14, irq11:9], irq[7:3] interrupt request input the irq signals provide both system board components and isa bus i/o devices with a mechanism for asynchronously interrupting the cpu. la23/ dcs3b#, la22/ dcs1b#, la21/ dcs3a#, la20/ dcs1a#, la[19:17]/ da[2:0] multifunctional pins bidirectional isa bus cycles unlatched address the la[23:17] address lines are bidirectional and allow accesses to physical memory on the isa bus up to 16 mbytes. pci ide cycles chip select dcs1a#, dcs3a#, dcs1b# and dcs3b# are for the ata command register block and correspond directly to cs1fx#, csf3x#, cs17x#, and cs37x# on the primary ide connector, respectively. pci ide cycles disk address da[2:0] are used to indicate which byte in either the ata command or control block is being accessed. the value driven on the la bus is the address stored in the ad address register during pci-initiated cycles and the refresh counter during non-isa bus master refresh cycles. the la pins are outputs when master# is high and are inputs when it is low. master# / mirq2 multifunctional pin input isa master cycle indicator an external bus master device asserts master# to indicate that it has control of the bus. plug and play interrupt request 2 mirq2 is a steerable interrupt request for on-board devices.
4-8 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information memcs16# 16-bit memory chip select input isa 16-bit slave memory devices drive this line low to indicate support for 16-bit memory bus cycles. this line is sampled to determine when a 16-bit to 8-bit conversion is needed for cpu accesses. conversion is performed when the AMD-645 peripheral bus controller requests a 16-bit memory cycle and memcs16# is sampled high. a command delay of one clock cycle is inserted and the cycle becomes four wait states long. if memcs16# is sampled low, a memory access is performed in one wait state with no command delays inserted. memcs16# is ignored for dma and refresh cycles. memr# memory read bidirectional memr# is the command to a memory slave that permits it to drive data onto the isa data bus. this signal is an input when an external bus master is in control and an output at all other times. memw# memory write bidirectional memw# is the command to a memory slave that permits it to latch data from the isa data bus. this signal is an input when an external bus master is in control and an output at all other times. refresh# refresh bidirectional as an output, refresh# indicates a refresh cycle is in progress. it is asserted by the AMD-645 peripheral bus controller whenever a refresh cycle is initiated. as an input, refresh# is driven by 16-bit isa bus masters to indicate a refresh cycle. rstdrv reset drive output rstdrv is the reset signal to the isa bus. it is generated from the received rst signal and is synchronized to pclk, though it is used for the isa bus. sa[15:0]/ dd[15:0] system address bus/ide data bus bidirectional these pins serve as the address bus in isa operation and the data bus in ide operation.
signal descriptions 4-9 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information sa16 system address bus bidirectional this signal is isa address bit 16. sbhe# system byte high enable bidirectional when asserted, sbhe# indicates that a byte is being transferred on the upper byte of the isa data bus (sd[15:8]). sbhe# is negated during refresh cycles. sd[15:8]/ gpi[15:8] gpo[15:8] multifunctional pins bidirectional isa system data sd[15:8] provide the high order data path for devices residing on the isa bus. the low order isa path, sd[7:0], is multiplexed with xd[7:0] (see page 4-13). general-purpose inputs if the gpio3_cfg bit is cleared (function 3, offset 40h, bit 6), these pins function as gpi[15:8] and pin 92 serves as read enable gpi_re#. general-purpose outputs if the gpio4_cfg bit is cleared (function 3, offset 40h, bit 7), these pins function as gpo[15:8] and pin 92 serves as write enable gpi_we. smemr# standard memory read output smemr# is the command that permits a slave to drive data residing below the 1 mbyte region onto the isa data bus. smemw# standard memory write output smemw# is the command that permits a slave to latch data residing below the 1 mbyte region from the isa data bus. tc terminal count output the AMD-645 peripheral bus controller asserts tc to dma slaves to indicate that one of the dma channels has transferred all data. spkr/ power-up strap multifunction pin bidirectional speaker drive after reset, this pin functions as the spkr signal, which is the output of counter 2.
4-10 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information power-up strapping at reset, if this pin is strapped low, the ide i/o base is fixed. if the pin is strapped high, the ide i/o base is flexible. 4.3 ultra dma-33 enhanced ide interface note: the ide address, data, and drive select pins are multiplexed with the isa bus la and sa pins and are described in section 4.2. ddacka# disk dma acknowledge a output s ddacka# is the primary ide channel dma acknowledge. the AMD-645 peripheral bus controller responds to ddrqa either to acknowledge that data has been accepted or to inform that data is available. ddackb# disk dma acknowledge b output ddackb# is the secondary ide channel dma acknowledge. the AMD-645 peripheral bus controller responds to ddrqb either to acknowledge that data has been accepted or to inform that data is available. ddrqa device dma request a input ddrqa is the primary ide channel dma request. a device asserts ddrqa when it is ready to read or write dma data. ddrqb device dma request b input ddrqb is the secondary ide channel dma request. a device asserts ddrqb when it is ready to read or write dma data. diora#/ hdmardya#/ hstrobea# multifunction pin output eide mode device i/o ready a diora# is the primary ide channel drive write strobe. the falling edge of diora# enables the transfer of data from a register or data port of the drive onto the ide data bus, dd[15:0]. the rising edge of diora# latches the data. ultra dma mode host dma ready hdmardya# functions as the primary channel input flow control. the host can assert hdmardya# to pause input data transfers.
signal descriptions 4-11 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information ultra dma mode host strobe a hstrobea functions as the primary channel output strobe. the host can stop hstrobea to pause output data transfers. diorb#/ hdmardyb#/ hstrobeb multifunction pin output eide mode device i/o ready b diorb# is the secondary ide channel drive write strobe. the falling edge of diorb# enables the transfer of data from a register or data port of the drive onto the ide data bus, dd[15:0]. the rising edge of diorb# latches the data. ultra dma mode host dma ready b hdmardyb# functions as the secondary channel input flow control. the host can assert hdmardyb# to pause input data transfers. ultra dma mode host strobe b hstrobeb functions as the secondary channel output strobe. the host can stop hstrobeb to pause output data transfers. diowa#/ stopa multifunction pin output eide mode device i/o write a diowa# is the primary ide channel drive read strobe. the rising edge of diowa# clocks data from the ide data bus (dd[15:0]) into either a register or the data port of the drive. ultra dma mode stop a stopa halts data transfer in the primary channel. the host asserts stopa before an ultra dma burst is initiated and negates stopa before an ultra dma burst is transferred. the host asserts stopa during or after data transfer in ultra dma mode to signal the termination of the burst. diowb#/ stopb disk i/o write b output eide mode device i/o write b diowb# is the secondary ide channel drive write strobe. the rising edge of diowa# clocks data from the ide data bus (dd[15:0]) into either a register or the data port of the drive.
4-12 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information ultra dma mode stop b stopb halts data transfer in the secondary channel. the host asserts stopb before an ultra dma burst is initiated and negates stopb before an ultra dma burst is transferred. the host asserts stopb during or after data transfer in ultra dma mode to signal the termination of the burst. drdya#/ ddmardya#/ dstrobea multifunction pin input eide mode device ready a drdya# is the primary channel device ready indicator. a device negates drdya# to extend the AMD-645 peripheral bus controller read or write cycle when it is not ready to respond to a data transfer request. when drdya# is negated, it is in a high impedance state. ultra dma mode device dma ready a ddmardya# is the primary channel output flow control. a device can assert ddmardya# to pause output transfers. ultra dma mode device strobe a dstrobea is the primary channel input data strobe. a device can stop dstrobea to pause input data transfers. drdyb#/ ddmardyb#/ dstrobeb multifunction pin input eide mode device ready b drdyb# is the secondary channel device ready indicator. a device negates drdyb# to extend the AMD-645 peripheral bus controller read or write cycle when it is not ready to respond to a data transfer request. when drdyb# is negated, it is in a high impedance state. ultra dma mode device dma ready b ddmardyb# is the primary channel output flow control. a device can assert ddmardyb# to pause output transfers. ultra dma mode device strobe b dstrobeb is the primary channel input data strobe. a device can stop dstrobeb to pause input data transfers.
signal descriptions 4-13 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information soe# system address transceiver output enable output soe# controls the output enables of the 74f245 transceivers that interface the ide data bus (dd[15:0]) to the system address bus (sa[15:0]). master# drives the transceiver direction control with dd[15:0] connected to the a side of the transceivers and sa[15:0] connected to the b side. 4.4 xd bus interface romcs#/ kbcs# multifunctional pin output rom chip select in isa memory cycles, romcs# is the chip select to the rom bios. keyboard chip select in isa i/o cycles, kbcs# is the chip select to the external keyboard controller. xd[7:0]/ sd[7:0]/ extsmi[7:3]/ gpi[7:0]/ gpo[7:0]/ power-up straps multifunction pins bidirectional xd[7:0] connection to external x-bus devices such as bios rom. sd[7:0] low order data path for devices residing on the isa bus. these signals are multiplexed with xd[7:0] through a 74f245 transceiver. refer to the description of the xdir pin on page 4- 14 extsmi[7:3] external sci/smi ports. gpi[7:0] general-purpose inputs if configuration register function 3, offset 40h, bit 6 is cleared. gpo[7:0] general-purpose outputs if configuration register function 3, offset 40h, bit 7 is cleared.
4-14 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information power-up straps pins xd[7:0] are used as strap options during power-up (see configuration register function 0, offset 5ah on page 7-27). strapping low disables and strapping high enables the following functions: ? xd[7:4] rp[16:13] for internal kbc ? xd2 internal rtc ? xd1 internal ps/2 mouse ? xdo internal kbc xdir x-bus data direction output xdir is tied directly to the direction control of the 74f245 transceiver that buffers the x-bus data and isa-bus data. sd[7:0] connect to the a side of the transceiver and xd[7:0] connect to the b side. the output enable of the transceiver should be grounded. a high signal on sdir indicates that sd[7:0] drives xd[7:0]. 4.5 plug-n-play support the AMD-645 peripheral bus controller provides three interrupt request pins to support plug-n-play functions from non-pnp devices. these asynchronous interrupt requests are mappable to any of the interrupt channels. each pin has an alternate function which is selected in configuration register function 0, offset 59h (see page 7-26). mirq2/master# multifunction pin input plug-n-play interrupt request 2 isa master cycle indicator ( see page 4-7) mirq1/keylock multifunction pin input plug-n-play interrupt request 1 keylock keyboard lock input mirq0#/apiccs# multifunction pin input plug-n-play interrupt request 0
signal descriptions 4-15 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information apiccs# apic chip select this signal is provided for external io apic devices in symmetric multiprocessor implementations. 4.6 universal serial bus interface usbclk universal serial bus clock input usbdata0+ usb port 0 data + bidirectional usbdata0C usb port 0 data C bidirectional usbdata1+ usb port 1 data + bidirectional usbdata1C usb port 1 data C bidirectional 4.7 power management pwrbtn# power button input referenced to v dd -5vsb. pwrgd power good input pwrgd is connected to the powergood signal on the power supply. pwron power supply control output powered by v dd -5vsb. ri# ring indicator input this signal can be connected to external modem circuitry to allow the system to be reactivated by a received phone call. input referenced to v dd -5vsb.
4-16 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 4.8 power and ground agnd usb differential output ground power a vdd usb differential output power source v dd 3 power supply for the cpu i/o voltagepower this pin should be connected to the same voltage as the cpu i/o circuitry. v dd power supply of 4.75 v to 5.25 v power this supply is turned on only when the mechanical switch on the power supply is turned on and the pwron signal is conditioned high. v dd -5sb power supply power v dd -5sb is always available unless the mechanical switch of the power supply is turned off. if the soft-off state is not implemented, then this pin can be connected to v dd . v dd -pci pci voltage, 3.3 v or 5 v power gnd ground power 4.9 internal real-time clock osc oscillator input osc is a 14.31818-mhz clock used by the internal timers and the acpi timer. rtcx1/ irq8# multifunctional pin input rtcx1 when the internal rtc is enabled, this signal is the rtc crystal or oscillator input (32.768 khz.) irq8# when the internal rtc is disabled, irq8# is an input from an external keyboard controller.
signal descriptions 4-17 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information rtcx2/ rtccs# multifunctional pin output rtcx2 when the internal rtc is enabled, this signal is the rtc crystal or oscillator output (32.768 khz.) rtccs when the internal rtc is disabled, this signal is the external rtc chip select. vbat rtc battery input this signal is the battery input for internal rtc. 4.10 keyboard interface a20m# a20 mask output the AMD-645 peripheral bus controller a20m# is a direct connection to a20m# on the cpu. kbck/ ka20g multifunctional pin bidirectional keyboard clock when the internal keyboard controller is enabled, kbck is the clock to the keyboard interface. keyboard gate a20 when the internal keyboard controller is disabled, ka20g is the gate a20 output from the external keyboard controller. kbdt/ kbrc# multifunctional pin bidirectional keyboard data when the internal keyboard controller is enabled, kbdt is the data line to the keyboard interface. keyboard reset when the internal keyboard controller is disabled, kbrc# is a reset input from the external keyboard controller. keylock keyboard lock input keylock is the keyboard lock signal for the internal keyboard controller.
4-18 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information msck/ irq1 multifunctional pin bidirectional mouse clock when the ps/2 mouse is enabled, msck functions as the clock to the ps/2 mouse interface. irq1 when both the ps/2 mouse and the internal kbc are disabled, irq1 functions as interrupt request 1 from the external kbc. msdt/ irq12 multifunctional pin bidirectional mouse data when the ps/2 mouse is enabled, msdt functions as data to the ps/2 mouse interface. irq12 when the ps/2 mouse is disabled, irq12 functions as interrupt request 12 from the external kbc. 4.11 cpu interface cpurst cpu reset output the AMD-645 peripheral bus controller asserts cpurst to reset the cpu during power-up. ferr# numerical coprocessor error output ferr# is tied to the coprocessor error signal on the cpu. ignne# ignore error output ignne# is connected to the ignore error pin on the cpu. init initialization output the AMD-645 peripheral bus controller asserts init if it detects a shut-down special cycle on the pci bus, or if a soft reset is initiated by the register. intr cpu interrupt output intr is driven by the AMD-645 peripheral bus controller to signal the cpu that an interrupt request is pending and needs service.
signal descriptions 4-19 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information nmi non-maskable interrupt output nmi is used to force a non-maskable interrupt to the cpu. the AMD-645 peripheral bus controller generates an nmi when either serr# or iochk# is asserted. smi# system management interrupt output smi# is asserted by the AMD-645 peripheral bus controller to alert the cpu in response to selected power management events. stpclk# stop clock output stpclk# is asserted by the AMD-645 peripheral bus controller to the cpu in response to selected power management events. 4.12 general-purpose i/o gpio0/ extsmi0 multifunction pin bidirectional gpio0 general-purpose i/o. this pin sits on the v dd -5vsb power plane and is available in the soft-off state as well as regular operation. extsmi0 an external input signal to trigger an smi/sci to the cpu. gpio1/ extsmi1#/ i2cd1(clock) multifunction pin bidirectional gpio1 general-purpose i/o. extsmi1 an external input signal to trigger an smi/sci to the cpu. i 2 cd1 this pin can be used along with gpio2 as an i 2 c pair (software convention defines this pin as clock). gpio2/ extsmi2#/ i2cd2(data) multifunction pin bidirectional gpio2 general-purpose i/o.
4-20 signal descriptions AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information extsmi2 an external input signal to trigger an smi/sci to the cpu. i 2 cd1 this pin can be used along with gpio1 as an i 2 c pair (software convention defines this pin as data). gpio3/ extsmi3#/ gpi_re# multifunction pin bidirectional gpio3 general-purpose i/o (if configuration register function 3, offset 40h, bit 6 is set) extsmi3 an external input signal to trigger an smi/sci to the cpu. gpi_re read enable for general-purpose inputs (if configuration register function 3, offset 40h, bit 6 is cleared). this pin connects to the output enable pin (oe#) of the external fs244 buffers connecting sd[15:8] and xd[7:0] for gpi[15:0]. gpio4/ extsmi4#/ gpi_we# multifunction pin bidirectional gpio4 general-purpose i/o (if configuration register function 3, offset 40h, bit 7 is set). extsmi4 an external input signal to trigger an smi/sci to the cpu. gpi_we write enable for general-purpose inputs (if configuration register function 3, offset 40h, bit 7 is cleared). this pin connects to the latch enable pin (oe#) of the external fs244 buffers connecting sd[15:8] and xd[7:0] for gpi[15:0].
functional operations 5-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5 functional operations 5.1 pci bus-initiated accesses the AMD-645 peripheral bus controller is responsible for decoding pci bus requests from pci bus masters, initiating the requested actions, and responding in the manner required by the pci bus protocol. 5.1.1 overview the AMD-645 peripheral bus controller responds to pci bus cycles in one of the two following ways. positive decode if the pci address matches an address block defined in the AMD-645 peripheral bus controller as positive isa decode space, the AMD-645 peripheral bus controller claims the cycle and asserts devsel# after the first clock following frame# first sampled asserted. this same devsel# assertion time occurs during all configuration cycles when idsel is sampled active. subtractive decode the AMD-645 peripheral bus controller is assumed to be the only agent responsible for any pci cycles which are not claimed by other pci targets. it determines if a pci cycle is unclaimed by the process of subtractive decoding. if a pci address does not match any address block defined in the AMD-645 peripheral bus controller, and the devsel# input is sampled inactive for three clocks after frame# is first sampled asserted, the AMD-645 peripheral bus controller responds to the cycle. devsel# timing for subtractive decoding is fixed at medium time slot. the AMD-645 peripheral bus controller also generates an isa bus cycle for any memory or i/o cycle claimed by the isa function.
5-2 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.1.2 bus cycle decoder table 5-1 shows how the AMD-645 peripheral bus controller decodes the pci command signals when an initiator generates a bus cycle. 5.2 pci bus commands the AMD-645 peripheral bus controller responds to the pci bus commands according to the descriptions in the following sections. 5.2.1 interrupt acknowledge the AMD-645 peripheral bus controller releases an 8-bit interrupt vector on ad[7:0] in respond to an interrupt acknowledge cycle. table 5-1. pci bus command encoding and types c/be3# c/be2# c/be1# c/be0# command type 0000interrupt acknowledge 0001special cycles 0010i/o read 0011i/o write 0100reserved 0101reserved 0110memory read 0111memory write 1000reserved 1001reserved 1010configuration read 1011configuration write 1100memory read multiple 1101dual address line 1110memory read line 1111memory write and invalidate
functional operations 5-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.2.2 special bus cycles the AMD-645 peripheral bus controller monitors all special bus cycles. 5.2.3 i/o read/write all i/o accesses not claimed by other pci targets through the assertion of devsel# are passed to the isa bus controller and executed as standard isa bus cycles. the AMD-645 peripheral bus controller steers the data between the pci ad bus and the isa sd bus or the ide data bus, as required by each cycle type. if the access is to an on-chip i/o location, then the data is steered between the ad bus, the sd bus, and the selected internal location, as required by the cycle type. the AMD-645 peripheral bus controller asserts trdy# upon completion of all isa bus accesses. in the case of i/o reads, valid data is placed on the pci ad bus before trdy# is asserted. the timing of a pci cycle forwarded to the isa bus is shown in figure 5-3 on page 5-6. the i/o-related isa bus signals are ior#, iow#, and iocs16#. ior# is active during an i/o read cycle, while iow# is active during a write cycle. iocs16# asserted indicates that a 16-bit slave is responding. a high level on iocs16# indicates that an 8-bit slave is responding. the AMD-645 peripheral bus controller decodes the pci commands and issues a command in the middle of tc or at the beginning of tw1, depending on the setting of bit 7 of the isa bus control register, function 0, offset 40h (see page 7-17). an 8-bit cycle is four wait states long while a 16-bit cycle has no wait states if the default configuration is used. additional wait states can be inserted by setting bit 5 or bit 4 of the isa bus control register, or by negating iochrdy. figure 5-1 illustrates i/o accesses for both read and write, including the insertion of wait states.
5-4 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-1. i/o access for 32-bit or 24-bit accesses to 16-bit isa bus slaves, or for 32- bit, 24-bit, or 16-bit accesses to 8-bit isa bus slaves, the AMD-645 peripheral bus controller generates multiple isa bus cycles for each pci bus cycle in order to match the size of the access requested by the pci initiator. requests for non- contiguous bytes are handled by converting the access to the appropriate isa bus cycles. the conversion of a single pci cycle to multiple isa cycles is invisible to the pci interface, except for the increased latency required to complete the operation. the AMD-645 peripheral bus controller converts a cpu request for 16-bit data from an 8-bit peripheral into two 8- bit cycles as depicted in figure 5-2. 8-bit operation 16-bit operaton bclk bale la[23:17] sa[19:0] ior#, iow# iocs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
functional operations 5-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-2. i/o cycle 16-bit to 8-bit conversion the slot address lines sa1, sa0, and sbhe# function the same for i/o reads and writes as they do for memory reads and writes. 5.2.4 memory read/write the AMD-645 peripheral bus controller directs all memory accesses not claimed by other targets to the isa bus. the AMD-645 peripheral bus controller steers data between the pci ad bus and the isa data bus as required by the requested cycle. the AMD-645 peripheral bus controller supports bursting (multiple read or write transactions). if frame# and irdy# even byte odd byte blck bale la[23:17] sa19-sa0 ior#, iow# sa0 sbhe# iocs16# iochrdy sd[15:8] (read) sd[15:8] (write) blck
5-6 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information are asserted at the same time, the AMD-645 peripheral bus controller will not disconnect if it is able to complete the data phase within specified latency requirements. target latency is limited to 16 pci clocks from the assertion of frame# for initial accesses, and limited to eight pci clocks from the end of the previous data phase for subsequent accesses of a burst cycle. all non-posted isa writes and all isa reads use delayed transactions to meet these latency requirements. figure 5-3 shows the timing of a non-posted pci cycle forwarded to the isa bus. figure 5-3. non-posted pci-to-isa access if the AMD-645 peripheral bus controller is unable to complete the initial data phase within the required initial latency, it begins a delayed transaction and terminates with retry by asserting stop# without asserting trdy# at the end of the initial data phase. if the next data phase in a burst cannot be completed within the required incremental latency, the AMD-645 peripheral bus controller disconnects by asserting trdy# and stop# at the end of the current data phase. memory write posting in the AMD-645 peripheral bus controller is enabled by setting the post memory write enable bit, configuration register function 0, offset 46h, bit 0 (see pclk sysclk frame# irdy# trdy# stop# ad[31:0] (read) ad[31:1] (write) bale cmd
functional operations 5-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information page 7-21). when write posting is enabled, trdy# is asserted one clock cycle after both frame# and irdy# are sampled active. the AMD-645 peripheral bus controller completes the access on the isa bus. attempts to access the isa bus before the posted write is complete must wait for the isa bus cycle to complete. the timing for a posted write cycle is shown in figure 5-4. figure 5-4. posted pci-to-memory write the memory-related isa bus control signals are memr#, smemr#, memw#, smemw#, and memcs16#. smemr# and smemw# are active only if the access is within the first mbyte of memory. the state of memcs16# at the beginning of bus cycle state tc determines whether the present cycle is 8-bit or 16-bit, as shown in figure 5-5. pclk bclk frame# irdy# trdy# stop ad[31:1] (write) bale memw# pclk
5-8 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-5. isa bus memory access cycle the command signals become active at the start of tc for 16- bit cycles, or in the middle of tc for 8-bit cycles. the falling edge of a command signal can be delayed by one or two bclks by setting bit 7 of the isa bus control register, function 0, offset 40h (see page page 7-17). under default settings, the command signals are negated at the beginning of tw5 for an 8- bit operation, and at the beginning of tw2 in the case of a 16- bit operation. it may be necessary to delay the rising edge of command signals by one bclk. this delay can be achieved by setting bit 5 of the isa bus control register. for slow peripherals, wait states may be inserted by pulling iochrdy low by the middle of tw4 for 8-bit cycles and by the beginning of tw2 for 16-bit cycles. the AMD-645 peripheral bus controller converts a pci bus master request for 16-bit, 24-bit, or 32-bit data from an 8-bit isa memory into two, three, or four 8-bit cycles, respectively. 8-bit operation 16-bit operaton bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
functional operations 5-9 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information a request for 32 bits from a 16-bit isa slave results in two 16- bit accesses. the AMD-645 peripheral bus controller also converts requests for non-contiguous bytes by converting the access to the appropriate isa bus cycles. these conversion cycles are shown in figures 5-6, 5-7, and 5-8. figure 5-6. isa bus memory cycle: 16-bit to 8-bit conversion even byte odd byte bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# sa0 sbhe# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
5-10 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-7. memory cycle 32-bit to 8-bit conversion bclk bale la[23:17] sa[19:0] memr#, memw# memr#, smemw# sa1 sa0 sbhe# memcs163 iochrdy sd[15:8] (read) sd[15:8] (write) bclk byte 3 operation byte 0 operation byte 1 operation byte 2 operation
functional operations 5-11 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-8. memory cycle 32-bit to 16-bit conversion be=0000 be=1001 bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# sa1 sa0 sbhe# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) byte 2 oper byte 1 oper byte 2,3 oper bclk byte 0,1 oper
5-12 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information if the memory accessed is rom, the timing is different for command signals memr# and smemr#, which become active at the falling edge of bale. both 8-bit and 16-bit rom access cycles are three wait states long. they can be programmed to be zero or one wait states using bit 1 of the isa bus controller configuration register (see page 7-17). figure 5-9 shows a rom access. figure 5-10 shows requests for 32 bits of data from 8-bit roms. figure 5-9. rom access 8-bit read 16-bit read bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# sa0 sbhe# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
functional operations 5-13 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-10. rom cycle 32-bit to 8-bit conversion bclk bale la23-la17 sa19-sa0 memr#,memw# sa1 sa0 sbhe# memcs16# iochrdy sd15-sd8 read sd15-sd8 write byte 0 operation byte 1 operation byte 2 operation byte 3 operation bclk bclk bclk
5-14 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information sa1, sbhe#, and sa0 are a direct decode of the c/be[3:0]# inputs from the pci bus. during a conversion cycle, sbhe# and sa0 are toggled so that the appropriate bytes are accessed, as shown in table 5-2. 5.2.5 configuration read/write as a target, the AMD-645 peripheral bus controller responds to both read and write configuration cycles. access to the configuration address space requires device selection decoding to be done externally via the idsel pin, which functions as a chip select signal. the idsel signal associated with device number 0 is connected to ad16, idsel of device number 1 is connected to ad17, and so forth. the connection of the AMD-645 peripheral bus controller idsel is system-specific, but the recommended connection is to ad18. if the AMD-645 peripheral bus controller is selected during a pci master-initiated configuration cycle, devsel# is asserted two clocks after frame# assertion. on pci-to-configuration register reads, the AMD-645 peripheral bus controller drives the requested configuration register data onto ad[31:0], asserts trdy# four clocks after frame# is asserted, and negates trdy# and devsel# one clock after irdy# is asserted. on pci-to-configuration register writes, the AMD-645 peripheral bus controller asserts trdy# four clocks after frame# is asserted or two clocks after irdy# is asserted, whichever is later. data is strobed into the configuration registers the cycle before trdy# is asserted. the timing of these cycles is shown in figures 5-11 and 5-12. table 5-2. isa byte and word accesses sbhe# sa0 description 0 0 16-bit 1 0 8-bit, lsb 0 1 8-bit, msb 1 1 undefined
functional operations 5-15 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-11. configuration read cycle figure 5-12. configuration write cycle address data cfg-rd be's pclk frame# ad idsel c/be[3:0]# irdy# trdy# stop devsel# pclk address data-in cfg-wr be's pclk frame# ad idsel c/be[3:0]# irdy# trdy# stop devsel# pclk
5-16 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.2.6 memory read multiple the memory read multiple command is treated the same as a memory read command by the AMD-645 peripheral bus controller. 5.2.7 dual address line the AMD-645 peripheral bus controller supports 32-bit addressing only, so dual address line commands are ignored. there is no response. 5.2.8 memory read line the AMD-645 peripheral bus controller treats the memory read line command just as it does the memory read command. 5.2.9 memory write invalidate the AMD-645 peripheral bus controller treats the memory write invalidate command just as it does the memory write command.
functional operations 5-17 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.3 pci bus features 5.3.1 back-to-back cycles as a target, the AMD-645 peripheral bus controller can respond to fast back-to-back cycles as described in the pci specification. all back-to-back cycles by the same initiator require at least one turn-around cycle, except when both transactions are writes to the same target. 5.3.2 subtractive decoding subtractive decoding ensures that every pci bus access gets a response. any pci cycle not claimed by other targets and whose address is not defined in the AMD-645 peripheral bus controller address block is forwarded to the isa bus. the timing for subtractive decoding is shown in figure 5-13. figure 5-13. subtractive decode timing 5.3.3 isa bus control register bus control options can be programmed via the isa bus control register, function 0, offset 40h (see page 7-17). this register controls the number of wait states to be inserted in the 8-bit and 16-bit slot cycles and determines the output drive of the slot bus buffers. more than five wait states are possible if iochrdy is pulled low before the last normal wait state. 1234567 fast med slow sub pclk frame# irdy# trdy# devsel# 1234567 pclk
5-18 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.4 isa bus-initiated cycles the AMD-645 peripheral bus controller is responsible for forwarding isa bus cycles to the pci bus. the only two initiators on the isa bus are the dma controller and the isa bus master. the dma controller can only generate memory read and write cycles, while an isa master can generate i/o as well as memory cycles. masters must repeat a read or write transaction that is terminated with retry. masters must assert irdy# within eight clocks during all data phases. ideally, irdy# is asserted with no delay on all data phases. 5.4.1 dma-initiated cycles in the pc/at, dma transfers occur between peripherals and memory at a data width of either 8 bits or 16 bits. of the seven external dma channels available, four are used for 8-bit transfers and three for 16-bit transfers. one byte or word is transferred in each dma cycle. normally, an add-on card issues a dma request by asserting one of the drq[7:5] or drq[3:0] signals. when the AMD-645 peripheral bus controller detects this request and the request is a read from memory, it generates a request to the pci arbiter. when it receives a pci grant, the AMD-645 peripheral bus controller initiates a pci memory read transaction using the current dma address, prefetching all data within the addressed doubleword. when the transaction is complete, the AMD-645 peripheral bus controller asserts the corresponding dack# line to indicate a dma acknowledge. prefetch data is transferred in response to subsequent dma requests without further pci bus accesses. when the AMD-645 peripheral bus controller detects a memory write request, it asserts the corresponding dack# line to indicate the dma acknowledge, reads the data from the dma device, and merges the data into a single doubleword. when the last byte of the doubleword has been read, the
functional operations 5-19 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information AMD-645 peripheral bus controller generates a request to the pci arbiter. when it receives a pci grant, it starts a pci memory write transaction for the entire doubleword with appropriate byte enables. aen and bale go high after the dma is acknowledged and any pending isa bus cycle has completed. the dma address is placed on la[23:20] and sa[19:0]. two dmaclk cycles later, either memr# and iow# or memw# and ior# are asserted, depending on the direction of the transfer. if the isa command delay bit of the isa bus control register is set, memr# is asserted one dmaclk cycle earlier. the command remains active for three dmaclk cycles. the data transfer takes place on the rising edges of command signals. tc is activated before the end of the command if the transfer is from one 8-bit device to another or one 16-bit device to another. if the transfer is from a 16-bit device to an 8-bit device, the command signals are again asserted after a delay of two dmaclk cycles and the transfer is complete. figure 5-14 shows the timing for a typical dma transfer. due to concurrent pci and isa bus operation during dma, the timing on each bus is independent of the state of the other bus. the state of the data buffers determines when pci bus requests are generated and when dma wait states are generated by negating iochrdy. pci bus requests to the arbiter during memory reads are issued only when the memory read buffer is empty. during memory writes, pci bus requests are issued when the msb of the memory write buffer is full. iochrdy is negated when the memory read buffer is empty during memory reads, or when the memory write buffer is full during memory writes.
5-20 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-14. dma transfer cycle 5.4.2 isa bus master initiated cycles an isa bus master card issues a dma request on the isa bus, as shown in figure 5-15, using a dma channel which has been placed in the cascade mode. the AMD-645 peripheral bus controller responds with an acknowledge signal in the same manner as for a dma cycle. the add-on card then gains control of the isa bus by asserting the master# signal. unlike dma cycles, there can be multiple data transfers in master mode. an isa bus master can generate both memory and i/o accesses. bclk dclk (internal) drq[3:0] hold (internal) hlda (internal) bale, aen dack[7:5]#, la[23:16] sa[15:8] sa[7:2] sa[1:0] ior#, memr# memw#/iow# tc smemw# bclk dclk (internal) bclk dclk (internal) dack[3:0]#
functional operations 5-21 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-15. isa bus master arbitration timing when the AMD-645 peripheral bus controller detects memr# or memw# active, it starts the pci cycle, asserts frame#, and negates iochrdy. this procedure guarantees that the isa cycle will not complete before the pci cycle has provided or accepted the data. iochrdy is asserted when irdy# and trdy# are sampled active. figure 5-16 shows an isa bus master memory read, and figure 5-17 shows a isa bus master memory write. the isa bus and pci bus operate concurrently. a separate pci bus request is issued for each isa master command and the pci bus ownership is relinquished after the transaction is completed. the AMD-645 peripheral bus controller converts isa bus master i/o cycles into pci i/o cycles. the timing of these cycles is similar to that of the memory cycles shown in figures 7-16 and 7-17, with the single substitution of ior# and iow# for memr# and memw#. bclk dclk (internal) drq[7:5], drq[3:0] dack[7:5]#, dack[3:0]# master# aen bclk
5-22 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-16. isa bus master-to-pci memory (memory read) figure 5-17. isa bus master-to-pci memory (memory write) pclk bclk memr# sd[15:0] iochrdy frame# ad[31:0] (read) irdy# trdy# pclk pclk pclk pclk bclk memr# sd[15:0] iochrdy frame# ad31-ad0(read) irdy# trdy# pclk
functional operations 5-23 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.5 pci bus arbitration the signals preq# and pgnt# are used to control requesting and granting of the pci bus between the AMD-645 peripheral bus controller isa bridge and the amd-640 system controller. 5.6 i/o and memory mapping the AMD-645 peripheral bus controller decodes pci bus addresses to determine the destination of a pci memory or i/o request. the AMD-645 peripheral bus controller address decoder distinguishes five general regions for memory or i/o accesses. the region selected is a function of the pci address, the pci cycle type, and the values placed in the configuration registers that control memory mapping. the five general regions are described in the following paragraphs. ide bus i/o location the AMD-645 peripheral bus controller generates an ide bus access cycle via positive decoding and responds to the cycle when it recognizes an ide target address. bus master ide register i/o location an internal i/o access cycle is generated via positive decoding to the appropriate bus master ide register i/o block, and is responded to by the AMD-645 peripheral bus controller when it recognizes a bus master ide register target address. the base address of the bus master ide registers is set by the configuration base registers and the size is fixed at 16 bytes (8 bytes for each channel). isa bus i/o location (on-chip) an isa bus i/o access cycle is generated via subtractive decoding and is responded to by the AMD-645 peripheral bus controller when it recognizes an on-chip address during the isa bus cycle. isa bus i/o location (off-chip) a standard isa bus i/o access cycle is generated via subtractive decoding when no other pci slave responds to a pci i/o cycle. data is passed between the pci data bus (ad[31:0]) and the isa data bus (sd[15:0]). romcs#/kbcs# is asserted to select the keyboard controller if the i/o address is port 60h or port 64h.
5-24 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information isa bus off-board memory location standard 8-bit or 16-bit isa bus cycles are generated when the AMD-645 peripheral bus controller detects a memory access in the isa slot bus address range. data is passed between the pci data bus (ad[31:0]) and the isa data bus (sd[15:0]). the AMD-645 peripheral bus controller determines off-board memory locations through subtractive decoding of a pci-to-isa access (when none of the other targets asserts devsel#). if the isa address is defined as a rom region, romcs#/kbcs# is asserted. 5.6.1 i/o mapping i/o addresses that are not inhibited by devsel# are run as isa bus cycles. the data steering is based on the actual i/o addresses, depending on whether the i/o location is on-chip or off-chip. on-chip i/o for on-chip centralized and distributed dma devices, the isa bus cycle is run normally. only the steering on read cycles is affected. isa bus masters have access to all on-chip registers. the centralized dma i/o locations are at a fixed address, as shown in table 5-3, while the distributed dma i/o locations are at a programmable base address. sa bus i/o all i/o write cycles drive the data from the ad bus onto the sd bus and generate an iow# strobe. all i/o read cycles drive data from the sd bus onto the ad bus and generate an ior# table 5-3. i/o fixed address mapping address device location 0000h C 000fh dma#1 on-chip or pci bus 0080h C 008fh dma page registers on-chip 00c0h C 00dfh dma#2 on-chip or pci bus 0170h C 0177h ide channel 2 ide bus 01f0h C 01f7h ide channel 1 ide bus 0376h ide channel 2 ide bus 03f6h ide channel 1 ide bus 0010h C 007fh, 0090h C 00bfh, 00e0h C 016fh, 0178h C 01efh, 01f8h C 0375h, 0378h C 03f5h, 03f8h C ffffh general i/o locations pci/isa bus
functional operations 5-25 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information strobe. the AMD-645 peripheral bus controller drives data onto the sd bus during all on-chip reads, while the sd bus is the data source for all other i/o reads. 5.6.2 memory mapping memory accesses are divided into pci memory, rom, and isa bus memory accesses. table 5-4 shows the various memory regions and the destinations (pci, rom, or isa) supported by the AMD-645 peripheral bus controller. when a pci memory access is generated, one of the following events will occur. n if the devsel# input is sampled active within the fast, medium, or slow sample periods, the AMD-645 peripheral bus controller is deselected and a pci target device completes the cycle. n if the devsel# input is not sampled active within the fast, medium, or slow sample periods, the AMD-645 peripheral table 5-4. memory address mapping range address destination comments 0 to 786 kbytes 0_0000h C b_ffffh pci bus space isa bus space selected by active devsel# (by subtractive decode) 786kbytes to 960kbytes c_0000h C e_ffffh pci bus space isa bus space isa rom space selected by active devsel# (by subtractive decode) or selected by rom decode control 960kbytes to 1 mbyte f_0000h C f_ffffh isa bus space isa rom space (by subtractive decode) 1 mbyte to 15.875 mbytes 10_0000h C fd_ffffh pci bus space isa bus space selected by active devsel# (by subtractive decode) 15.875 mbytes to 16 mbytes fe_0000h C ff_ffffh pci bus space isa bus space selected by active devsel# (by subtractive decode) 16 mbytes t0 128 mbytes 100_0000h C 7ff_ffffh pci bus space aliased isa bus space selected by active devsel# (by subtractive decode) 128 mbytes to (4 gbytes C 512 kbytes) 8000_0000h C fff7_ffffh pci bus space aliased isa bus space selected by active devsel# by subtractive decode only (4gbytes C 512kbytes) to 4 gbytes fff8_0000h C ffff_ffffh isa rom space (by subtractive decode) or selected by rom decode control
5-26 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bus controller executes a subtractive decode which directs the access to the isa bus. when a master mode or dma isa memory access is generated, the AMD-645 peripheral bus controller initiates a pci cycle. if devsel# is not asserted within the fast, medium, or slow sample periods, the AMD-645 peripheral bus controller executes a subtractive decode which directs the access to the isa bus, and iochrdy is re-asserted to allow the isa cycle to complete. isa memory all memory accesses below 16 mbytes not accepted by pci bus devices through the assertion of devsel# are directed to the isa bus. the AMD-645 peripheral bus controller asserts devsel# for the cycles and generates standard isa cycles. it also provides the data latching and steering logic to allow the pci initiator to perform 8-bit, 16-bit, 24-bit, or 32-bit accesses to either 8-bit or 16-bit isa memory devices. accesses to the pci bus performed subtractively above 16 mbytes alias to the 24-bit isa bus addresses. pci accesses to these regions should be performed only if no dma or master mode cycles ever access the referenced locations, because a slot bus memory device may occupy the same aliased address an pci bus memory and bus contention would occur. access to system rom is provided in the top 512 kbytes of the aliased isa bus address space for correct reset vectoring. 5.6.3 system rom memory mapping setting of the bits in rom decode control enable different address ranges to be included in the romcs# decode. all pci accesses in the highest 512 kbytes of each 16 mbyte memory space (xxf80000h to xxffffffh) are always system rom accesses. system rom accesses are a subset of isa bus accesses. standard isa bus accesses are generated on system rom accesses, with the following differences: n romcs# is always asserted on system rom accesses. xdir is set to reflect the cycle type, read or write. n additional isa bus wait states can be programmed for system rom accesses via the rom wait states bit of the isa bus control register.
functional operations 5-27 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the AMD-645 peripheral bus controller provides the data latching and steering logic to allow the initiators to perform 8- bit, 16-bit, 24-bit, or 32-bit accesses to 8-bit system roms. it also performs the required isa bus cycles to assemble and latch the appropriate data and to present it to the pci initiator as requested. system rom is also accessible by isa bus masters and dma cycles. video rom and fixed disk rom, memory range c0000h to cffffh, can be defined to be in the system rom range using bits 7C0 of the rom decode control register (function 0, offset 43h). the programmable values of these bits are shown in table 5-5. setting the indicated bit enables the address range shown to be included in the romcs# decode. subtractive decodes are always performed, and the rom access may be inhibited by a pci target that is asserting devsel# and claiming the cycle. flash memory support support for programmable flash memory is provided by enabling write cycles to the bios rom regions that reside on the x-bus. bit 0 of the isa bus control register (function 0 offset 40h) is provided to enable write cycle generation. table 5-5. rom decode control register bit value address range enabled bit 7 = 1 fffe 0000h C fffeffffh enabled bit 6 = 1 fff80000h C fffdffffh enabled bit 5 = 1 000e8000h C 000e ffffh enabled bit 4 = 1 000e0000h C 000e7fffh enabled bit 3 = 1 000d8000h C 000d ffffh enabled bit 2 = 1 000d0000h C 000d7fffh enabled bit 1 = 1 000c8000h C 000c ffffh enabled bit 0 = 1 000c0000h C 000c7fffh enabled
5-28 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.7 clock generation the clocks described in the following paragraphs are used or generated by the AMD-645 peripheral bus controller. pclk this input signal is the pci clock used to synchronize the interface to all pci bus devices. osc this input signal is a 14.318-mhz clock common to the isa bus signal osc. it is used by the internal rtc. bclk this output signal is the isa bus system clock. it is derived either by a division of pclk by 2, 3, 4, 5, 6, 10, or 12, or by a division of osc by 2. bclk timing is controlled by programming the isa clock control register, function 0, offset 42h (see page 7-18). bit 3 of this register, the isa clock select enable bit, is cleared at reset, forcing bclk to default to a value of = pclk/4. to program a different time value for bclk, take the following steps. 1. clear bit 3 of isa clock control register. 2. program bits 2C0, the isa bus clock select bits of this reg- ister, writing the value selected from table 5-6. 3. set bit 3 of isa clock control register. table 5-6. isa bus clock select bit programming bit 2 bit 1 bit 0 bclk value 0 0 0 pclk / 3 (default) 001pclk / 2 010pclk / 4 011pclk / 6 100pclk / 5 101pclk / 10 110pclk / 12 1 1 1 osc / 2
functional operations 5-29 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.8 direct memory access the dma controllers are 8237-compatible, have internal latches for latching the middle address bits output by the 8237 megacells on the data bus, and have 74ls612 memory mappers to generate the upper address bits. the dma logic controls transfers between an i/o channel and on-board or off-board memory. this logic generates a bus request to the pci bus when an i/o channel requests a dma operation. once a bus grant has been issued, and any pending access to the isa bus is completed, the dma controller drives the pci address bus and the slot address bus. dma transfers can occur over the full 16 mbyte range available on the slot bus and the entire 32-bit address range of the pci bus. 5.8.1 dma controllers the AMD-645 peripheral bus controller supports seven dma channels using two 8237 equivalent megacells capable of running at bclk. this option is programmable via the type f dma control register (function 0, offset 45h). dma controller 1 contains channels 0 through 3. these channels support 8-bit i/o adapters. they are used to transfer data between 8-bit peripherals and 8-bit or 16-bit memory. each channel can transfer data in 64-kbyte pages within the first 16 mbytes of the pci memory space. dma controller 2 contains channels 4 through 7. channel 4 is used to cascade dma controller 1, so it is not available externally. channels 5 through 7 support 16-bit i/o adapters to transfer data between these adapters and 16-bit system memory. each channel can transfer data in 128-kbyte pages within the first 16 mbytes of the pci memory space. channels 5, 6, and 7 are meant to transfer 16-bit words only and cannot address odd bytes in system memory. 5.8.2 dma controller registers the 8237 megacells can be programmed anytime pgnt# is inactive, i.e., when dma controllers are not in operation. table 5-7 lists the i/o addresses of all slave and master dma
5-30 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information controller registers that can be read or written in the 8237 megacells. channels 0C3 of the master and slave dma controllers control system dma channels 0C3. there are 16 master and slave dma controller registers. slave & master dma controllers ports c0hCdfh the slave and master dma controller ports are listed in table 5-7. when writing to a channels address or word count register, the data is written into both the base register and current register simultaneously. when reading a channel address or word count register, only the current address or word count can be read. the base address and base word count are not accessible for reading. the address and word count registers for each channel are 16- bit registers. the value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing flip-flop. this flip-flop can be cleared by the clear byte pointer flip-flop command. following this command, the first read/write to an address or word count register will read or write to the least significant byte of the 16- table 5-7. ports 00hC0fh master dma controller slave i/o address bits master i/o address bits register name access 0000 0000 1100 000x 0000 0000 000x 0000 ch 0 base/current address rw 0000 0000 1100 001x 0000 0000 000x 0001 ch 0 base/current count rw 0000 0000 1100 010x 0000 0000 000x 0010 ch 1 base/current address rw 0000 0000 1100 011x 0000 0000 000x 0011 ch 1 base/current count rw 0000 0000 1100 100x 0000 0000 000x 0100 ch 2 base/current address rw 0000 0000 1100 101x 0000 0000 000x 0101 ch 2 base/current count rw 0000 0000 1100 110x 0000 0000 000x 0110 ch 3 base/current address rw 0000 0000 1100 111x 0000 0000 000x 0111 ch 3 base/current count rw 0000 0000 1101 000x 0000 0000 000x 1000 status/command rw 0000 0000 1101 001x 0000 0000 000x 1001 write request wo 0000 0000 1101 010x 0000 0000 000x 1010 write single mask wo 0000 0000 1101 011x 0000 0000 000x 1011 write mode wo 0000 0000 1101 100x 0000 0000 000x 1100 clear byte pointer f/f wo 0000 0000 1101 101x 0000 0000 000x 1101 master clear wo 0000 0000 1101 110x 0000 0000 000x 1110 clear mask wo 0000 0000 1101 111x 0000 0000 000x 1111 r/w all mask bits rw note: not all address bits are decoded.
functional operations 5-31 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit register and the byte pointer flip-flop will toggle back to zero. the 8237 dma controller megacells allow the user to program the active level of the dreq and dack# signals to be low or high. because the two megacells are cascaded together internally on the chip, dreq should always be programmed active high and dack# active low. when programming the 16-bit channels (dma controller 2, channels 5, 6, and 7), the address written to the base register must be the real address divided by two. the base word count for these channels is the number of 16-bit words to be transferred, not the number of bytes, as is the case for the 8-bit channels (dma controller 1, channels 0, 1, 2, and 3). it is recommended that all internal locations in the 8237 megacells, especially the mode registers, should be loaded with some valid value, even if the channels are not used. 5.8.3 middle address bit latches the middle dma address bits are held in an internal 8-bit register. the dma controller drives the value to be loaded onto the internal data bus, then issues an address strobe signal to latch the data bus value into this register. an address strobe is issued at the beginning of a dma cycle and any time the lower 8-bit address increments across the 8-bit subpage boundary during block transfers. this register cannot be read or written to externally. it is loaded only from the address strobe signals from the megacells, and the outputs go only to the ad[16:8] pins. 5.8.4 page registers the AMD-645 peripheral bus controller uses two 74ls612 cells to generate the page registers for each dma channel. the page registers provide the upper address bits during dma cycles. dma addresses do not increment or decrement across page boundaries. page boundaries for the 8-bit channels (channels 0, 1, 2, and 3) are every 64 kbytes. page boundaries for the 16- bit channels (channels 5, 6, and 7) are every 128 kbytes. there are 32 8-bit registers between the 612 megacells.
5-32 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information page registers must be written at the i/o addresses shown in table 5-8 to select the correct page for each dma channel before any dma operations are performed. address locations between 080h and 08fh other than those shown in the table are not used by the dma channels, but can be read or written to by a pci bus master. the page register is used to set the values for ad[23:16] bus lines. in normal operation, zeroes are driven onto pci address bits ad[31:24] during dma cycles, making the AMD-645 peripheral bus controller backward-compatible with the pc/at standard. 5.8.5 dma address generation dma addresses are organized as upper, middle, and lower address portions. the upper address portion selects a specific page, and is generated by the page registers in the 74ls612 megacells. the page registers for each channel must be set up by the system before a dma operation. dma addresses do not increment or decrement across page boundaries. page sizes are 64 kbytes for 8-bit channels 0 through 3, and 128 kbytes for 16-bit channels 5 through 7. the dma page register values are output on pci address bus ad[31:16] (8-bit channels) and ad[31:17] (16-bit channels). the middle address portion, which selects a block within the page, is generated by the 8237 megacells at the beginning of a dma operation and any time the dma address increments or table 5-8. ports 80hC8fh dma page register access page register address dma channel i/o address bits 15C0 register name 87h 0 0000 0000 1000 0111 ch 0 dma page m[0] rw 83h 1 0000 0000 1000 0011 ch 1 dma page m[1] rw 81h 2 0000 0000 1000 0001 ch 2 dma page m[2] rw 82h 3 0000 0000 1000 1101 ch 3 dma page m[3] rw 8bh 5 0000 0000 1000 1111 ch 5 dma page m[5] rw 89h 6 0000 0000 1000 1011 ch 6 dma page m[6] rw 8ah 7 0000 0000 1000 1001 ch 7 dma page m[7] rw 8fh 4 0000 0000 1000 1010 ch 4 dma page m[4] rw
functional operations 5-33 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information decrements through a block boundary. the block size of an 8- bit channel is 256 bytes, while that of a 16-bit channel is 512 bytes. the middle address portion is output by the 8237 megacells onto the internal data bus during state s1. the internal middle address bit latches latch this value in. the middle address bit latches are output on pci address bits ad[15:8] for 8-bit channels and ad[16:9] for 16-bit channels. the lower address portion is generated directly by the 8237 megacells during dma operations, and the lower address bits are output on pci address bits ad[7:0] for 8-bit channels and ad[8:1] for 16-bit channels. sbhe# is configured as an output during all dma operations it is driven as the inversion of ad0 during 8-bit cycles, and forced low for all 16-bit dma cycles. table 5-9 shows the mapping from the dma subsystem signals to slot bus signals. table 5-10 shows the mapping of the AMD-645 peripheral bus controller dma subsystem signals to pci address bus signals.
5-34 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 5-9. dma addressing for isa bus accesses (dma/slot bus) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits m[7] la[23] la[23] m[6] la[22] la[22] m[5] la[21] la[21] m[4] s/la[20] s/la[20] m[3] s/la[19] s/la[19] m[2] s/la[18] s/la[18] m[1] s/la[17] s/la[17] m[0] s/la[16] ------- d[7] s/la[15] s/la[16] d[6] s/la[14] s/la[15] d[5] s/la[13] s/la[14] d[4] s/la[12] s/la[13] d[3] s/la[11] s/la[12] d[2] s/la[10] s/la[11] d[1] s/la[9] s/la[10] d[0] s/la[8] s/la[9] a[7] s/la[7] s/la[8] a[6] s/la[6] s/la[7] a[5] s/la[5] s/la[6] a[4] s/la[4] s/la[5] a[3] s/la[3] s/la[4] a[2] s/la[2] s/la[3] a[1] s/la[1] s/la[2] a[0] s/la[0] s/la[1] vss ------- s/la[0] a[0]# sbhe# ------- vss ------- sbhe#
functional operations 5-35 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 5-10. dma addressing for isa bus accesses (dma/pci ad bus) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits 0 ad[31] ad[31] 0 ad[30] ad[30] 0 ad[29] ad[29] 0 ad[28] ad[28] 0 ad[27] ad[27] 0 ad[26] ad[26] 0 ad[25] ad[25] 0 ad[24] ad[24] m[7] ad[23] ad[23] m[6] ad[22] ad[22] m[5] ad[21] ad[21] m[4] ad[20] ad[20] m[3] ad[19] ad[19] m[2] ad[18] ad[18] m[1] ad[17] ad[17] m[0] ad[16] ------- d[7] ad[15] ad[16] d[6] ad[14] ad[15] d[5] ad[13] ad[14] d[4] ad[12] ad[13] d[3] ad[11] ad[12] d[2] ad[10] ad[11] d[1] ad[9] ad[10] d[0] ad[8] ad[9] a[7] ad[7] ad[8] a[6] ad[6] ad[7] a[5] ad[5] ad[6] a[4] ad[4] ad[5] a[3] ad[3] ad[4] a[2] ad[2] ad[3] a[1] ------- ad[2] a[0] ------- be[1], be[0]
5-36 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.8.6 type f dma type f dma is supported on all channels. the channels may be individually enabled to provide type f dma timing, using the type f dma control register (function 0, offset 45h) as shown in table 5-11. therefore, configuration software needs to detect type f-capable devices and configure their channels only once after reset. when type f dma is enabled for a channel, type f dma transfers occur during the dack# for that channel. that is, the programmed timing parameters are ignored, dma cycles occur with zero wait states, and the dma clock is set equal to bclk. a[0]# ------- be[3], be[2] a[1] + a[0] be[0]# ------- a[1] + a#[0] be#[1] ------- a[1] + a[0] be#[2] ------- a#[1] + a#[0] be#[3] ------- table 5-10. dma addressing for isa bus accesses (dma/pci ad bus) (continued) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits table 5-11. type f dma control offset 45h type f dma control default bit 7 = 1 isa master/dma to pci line buffer 0 bit 6 = 1 enable dma type f timing on channel 7 0 bit 5 = 1 enable dma type f timing on channel 6 0 bit 4 = 1 enable dma type f timing on channel 5 0 bit 3 = 1 enable dma type f timing on channel 3 0 bit 2 = 1 enable dma type f timing on channel 2 0 bit 1 = 1 enable dma type f timing on channel 1 0 bit 0 = 1 enable dma type f timing on channel 0 0
functional operations 5-37 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-18. type f dma timing 5.8.7 dma channel mapping registers dma channel mapping allows the selection of any dma channel number for each plug-n-play dma request/acknowledge signal pair. the mapping register allows each plug-n-play dma pin pair to be connected to any dma channel. when a plug-n-play dma pin pair is connected to a dma channel, that channels normal isa pin pair is disabled so that the drq is ignored and the dack# is driven high. 5.8.8 ready control logic the ready input to each of the 8237 megacells is driven from the same source within the ready control logic. the AMD-645 peripheral bus controller ready control logic forces the preprogrammed number of wait states on every dma transfer. if needed, the external signal iochrdy goes into the ready control logic to extend transfer signals further. to add extra wait states, an external device should pull iochrdy low within the setup time before the second phase of the internal dma clock no later than the last forced wait state cycle. the current dma cycle is then extended by inserting wait states until iochrdy is returned high. iochrdy going high must s1 s2 s3 s4 s2 s3 s4 si bclk dclk (internal) drq bale, aen dack[7:5]#, dack[3:0]# ior# tc sd[15:0] bclk
5-38 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information meet the setup time at the beginning of a wait state or an extra wait state will be inserted before the dma controller transitions to state s4. figure 5-19. dma ready timing 5.8.9 external cascading an external dma controller or bus master can be attached to an at-compatible design through the AMD-645 peripheral bus controller dma controllers. to add an external dma controller, one of the seven available dma channels must be programmed in the cascade mode. this channels drq signal should then be connected to the external dma controllers hlda input. when one of the seven channels is programmed in the cascade mode and that channel is acknowledged, the AMD-645 peripheral bus controller will not drive the data bus, the command signals, or the address bus. an external device can become a bus master and control the system address, data, and command buses in much the same manner. to enable this control, one of the external channels must be programmed in the cascade mode. the external device then asserts the drq line for that channel. when that channels dack# line goes active, the external device can then pull the master# signal low. as in the dma controller cascading, the AMD-645 peripheral bus controller does not drive the address, data, and command signals while the cascaded channels dack# signal is active. setup dma rdy setup s2 s3 sw s4 si sw bclk dclk (internal) drq dack7-dack5#, ior# iochrdy dack3-dack0#
functional operations 5-39 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.9 distributed dma support distributed dma is pci bus mastering with a legacy- compatible programming mode. it offers upward compatibility for isa legacy devices in pci bus systems, providing a vast improvement in performance. each channel in the 8237 dma controller is mapped to an individual dma slice. the channel 0 base address register, current address, base count and current count, command, status, request etc. are mapped to dma slice dma0. each slice exists in a separate, non-overlapping i/o address space in the pci bus space. the distributed dma control register is located in function 0, offset 60hC6fh. each channel base address can be individually programmed and enabled. 5.10 ultra dma support ultra dma is a data transfer protocol for ata/atapi-4 to be used with read dma and write dma commands and data transfers for packet commands. the AMD-645 peripheral bus controller supports ultra dma transfer mode 0, 1 and 2. table 5-12 lists the ultra dma interface signals that appear on the ide drive cable interface. table 5-12. ultra dma interface signals signal source s signal source reset host csel host dd[15:0] bidirectional dmack# host dmarq device intrq device dior#/hdmardy#/ hstrobe host da[2:0] host diow#/stop host pdiag# device iordy/ddmardy#/ dstrobe device cs0#, cs1# host csel host dasp# device
5-40 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information hdmardy# is a flow control signal for ultra dma input data bursts. it is asserted by the host when it is ready to receive dma data. the host negates hdmardy3 to pause an ultra dma data in transfer. hstrobe is the strobe signal from the host for an ultra dma output data transfer. both edges of hstrobe latch data from dd[15:0] into the device. the host may stop toggling hstrobe to pause an ultra dma output data transfer. stop can be asserted by the host during or after data transfer in an ultra dma mode to signal the termination of the burst. ddmardy# is a flow control signal for output data bursts. it is asserted by the device when it is ready to receive dma data. the device negates ddmardy# to pause an ultra dma output data transfer. dstrobe is the strobe signal from the device for an ultra dma input data transfer. both edges of dstrobe latch data from dd[15:0] into the host. the device may stop toggling dstrobe to pause an ultra dma data in transfer. the ultra dma protocol has three timing modes mode 0, mode 1, and mode 2. only one ultra dma mode is active at any time. the identify device data specifies the highest timing mode of which a device is capable. devices reporting support for ultra dma transfer mode 2 must also support mode 0 and mode 1. the control signal strobe that latches data from dd[15:0] is generated by the same agent, either host or device, which drives the data onto the bus. several signal lines assume new functions when the ultra dma protocol is active. these signal lines revert to the definitions used for multiword dma transfers upon the termination of the ultra dma transfer. all control signals are unidirectional. a read dma or write dma command or data transfer for a packet command is accomplished through a series of input or output data bursts. each burst has three phases of operation, the burst initial phase, the data transfer phase, and the burst termination phase. the burst initial phase begin with the assertion of dmarq by the device and ends when the sender toggles strobe to transfer the first data word. the data transfer phase is then in
functional operations 5-41 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information effect until the burst termination phase, which begins either when the host asserts stop or the device negates dmarq. 5.10.1 ultra dma read burst command initiating a read burst figure 5-20 shows the timing for an ultra dma read burst. the device asserts ddrq to initiate a burst. the host asserts ddack# when it is ready to begin the requested burst. the host releases data, the device asserts dstrobe, and the host negates stop and asserts dmardy#. the device then drives the first word of the data transfer onto data. the data is transferred when the device negates dstrobe. the device continues to drive a data word onto data and toggles dstrobe to latch the data until the data transfer is complete or the burst is paused. figure 5-20. ultra dma-33 ide read burst pausing a read burst either the device or the host can pause a burst transfer, as shown in figure 5-21. the device pauses the read dma burst by halting dstrobe toggling, and resumes the burst by toggling dstrobe again. the host pauses a read burst by negating hdmardy# and resumes the burst by reasserting hdmardy#. t ui t env1 t li1 t ds1 t dh1 pclk ddrq (host) ddack# (host) stop (host) hdmardy# (host) dstrobe (drive) data
5-42 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-21. pausing a dma burst terminating a read burst. either the device or the host can terminate a burst. the device initiates termination of a read burst by halting dstrobe toggling and negating dmarq. the host responds by asserting stop and negating hdmardy#. the host then places the result of its crc (cyclic redundancy check) on data and negates ddack#. the data is latched in the device at the negating edge of ddack#. figure 5-22 shows the timing for read burst termination initiated by a device. figure 5-22. drive terminating a dma read burst trfs t rp pclk ddrq (drive) ddack# (host) for write ddmardy# (drive) hstrobe (host) for read stop (host) hdmardy# (host) t li4 t za4 t dvs4 t dvh4 crc pclk ddrq (drive) ddack# (host) stop (host) hdmardy# (host) data
functional operations 5-43 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the host initiates a read burst termination by negating hdmardy# and asserting stop, as shown in figure 5-23. the device negates ddrq. the host then places the result of its crc (cyclic redundancy check) on data and negates ddack#. the crc is latched in the device at the negating edge of ddack#. figure 5-23. host terminating dma burst during read command 5.10.2 ultra dma write burst command initiating a write burst figure 5-24 shows the timing for an ultra dma write burst. the device asserts ddrq to initiate a write burst. the host asserts ddack# when it is ready to begin the requested burst. the device asserts ddmardy# after the host has negated stop. the host drives the first word of the data transfer onto data. the data is transferred when the host toggles hstrobe. data is transferred at both edges of hstrobe until data transfer is complete or the burst is paused. t mli6 t za6 crc pclk ddrq (drive) ddack (host) stop (host) hdmardy# (host) data
5-44 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-24. ultra dma-33 ide write burst pausing a write burst either the device or the host can pause a dma write burst transfer, as shown in figure 5-21 on page 5-42. the device pauses a write burst by negating ddmardy# and resumes the burst by reasserting ddmardy#. the host pauses a write burst by halting hstrobe toggling and resumes the burst by toggling hstrobe again. terminating a write burst either the device or the host can terminate a write burst. the device initiates burst termination by negating ddmardy#. the host shall halts hstrobe toggling. the device negates ddrq, and the host responds by asserting stop. the host asserts hstrobe (if it is negated), places the result of its crc on data, and negates ddack#. the crc is latched in the device at the negating edge of ddack#. figure 5-25 shows a the timing for a drive terminating a write burst. t ui t env2 t ui t dvs2 t dvh2 pclk ddrq (drive) ddack# (host) stop (host) ddmardy# (dirve) hstrobe (host) data
functional operations 5-45 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 5-25. drive terminating dma burst during write command the host initiates burst termination by halting hstrobe toggling and asserting stop, as shown in figure 5-26. the device responds by negating ddrq and ddmardy#. the host asserts hstrobe (if it is negated), places the result of its crc (cyclic redundancy check) on data, and negates ddack#. the crc is latched in the device at the negating edge of ddack#. figure 5-26. host terminating dma burst during write command t li5a t li5b t mli5 t dvs5 t dvh5 crc pclk ddrq (drive) ddack# (host) stop (host) hstrobe (host) data t li7 t mil7 t dvs7 t dvh7 crc pclk ddrq (drive) ddack# (host) stop (host) hstrobe (host) data
5-46 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.10.3 slave dma channel each slave dma channel has a block of sixteen 8-bit registers which are defined in table 5-13. this block is locatable anywhere in the legacy 64k i/o space by programming the slave dma configuration register. all slave dma channels must have an identical programming model. the master dma is programmed with the base address of each slave dma by having a matching base address register for each channel. table 5-13. programming model for single slave dma channel slave address read/ write register name byte dma address word dma address por value b + 0h w base address 0 C 7 ch0 = 0000h ch1 = 0002h ch2 = 0004h ch3 = 0006h ch4 = 00c0h ch5 = 00c4h ch6 = 00c8h ch7 = 00cch xxh b + 0h r current address 0 C 7 ch0 = 0000h ch1 = 0002h ch2 = 0004h ch3 = 0006h ch4 = 00c0h ch5 = 00c4h ch6 = 00c8h ch7 = 00cch xxh b + 1h w base address 8 C 15 ch0 = 0000h ch1 = 0002h ch2 = 0004h ch3 = 0006h ch4 = 00c0h ch5 = 00c4h ch6 = 00c8h ch7 = 00cch xxh b + 1h r current address 8 C 15 ch0 = 0000h ch1 = 0002h ch2 = 0004h ch3 = 0006h ch4 = 00c0h ch5 = 00c4h ch6 = 00c8h ch7 = 00cch xxh b + 2h w base address 16 C 23 ch0 = 0087h ch1 = 0083h ch2 = 0081h ch3 = 0082h ch4 = n/a ch5 = 008bh ch6 = 0089h ch7 = 008ah xx b + 2h r current address 16 C 23 ch0 = 0087h ch1 = 0083h ch2 = 0081h ch3 = 0082h ch4 = n/a ch5 = 008bh ch6 = 0089h ch7 = 008ah xxh b + 3h w base address 24 C 31 n/a n/a b + 3h r current address 24 C 31 n/a n/a b + 4h w base word count 0 C 7 ch0 = 0001h ch1 = 0003h ch2 = 0005h ch3 = 0007h ch4 = 00c2h ch5 = 00c6h ch6 = 00cah ch7 = 00ceh xxh b +4h r current word count 0 C 7 ch0 = 0001h ch1 = 0003h ch2 = 0005h ch3 = 0007h ch4 = 00c2h ch5 = 00c6h ch6 = 00cah ch7 = 00ceh xxh
functional operations 5-47 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.10.4 dma control registers there are two physical dma controllers in a legacy pc system, one for byte transfers and one for word transfers, so there are at least two possible control registers for each register defined. the byte transfer channels are channels 0C3, and their registers are mapped to the byte dma control registers. the word transfer channels are channels 4C7, and their registers are mapped to the word dma control registers. channel 4 is used to connect the two dma devices together in an isa system, so it is not available as a separate channel. command register the functionality of this register is identical to the legacy dma controller, so data is passed through unchanged. b + 5h w base word count 8 C 15 ch0 = 0001h ch1 = 0003h ch2 = 0005h ch3 = 0007h ch4 = 00c2h ch5 = 00c6h ch6 = 00cah ch7 = 00ceh xxh b + 5h r current word count 8 C 15 ch0 = 0001h ch1 = 0003h ch2 = 0005h ch3 = 0007h ch4 = 00c2h ch5 = 00c6h ch6 = 00cah ch7 = 00ceh xxh b + 6h w base word count 16 C 23 n/a n/a b + 6h r current word count 16 C 23 n/a n/a b + 7h n/a reserved (note 1) b + 8h w command 0008h 00d0h 00h b + 8h r status 008h 00d0h x0h b + 9h w request 0009h 00d2h 00h b + ah n/a reserved (note 1) b + bh w mode 000bh 00d6h 00h b + ch w reserved (note 1) b + dh w master clear 000dh 00dah n/a b + eh n/a reserved (note 1) b + fh w single-channel mask 000ah 00d4h 00h b + fh r single-channel mask config cfh config efh 00h note: 1. reads return all zeroes. writes have no effect. table 5-13. programming model for single slave dma channel (continued) slave address read/ write register name byte dma address word dma address por value
5-48 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information mode register data bits 1C0 are reserved. they are written undefined by the master dma. the legacy dma controller expects the channel number encoded in these bits. each slave dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing the two undefined bits. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. request register data bits 1C0 are reserved. they are written undefined by the master dma. the legacy dma controller expects the channel number encoded in these bits. each slave dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing the two undefined bits. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. single-channel mask register in writes to this register, the master dma writes the new mask value in data bit 0. data bits 1, 2, and 3 are reserved and will be written undefined by the master dma. the legacy dma controller expects the channel number encoded in bits 1C0 and the mask bit passed in bit 2. each slave dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing bits 1C0. the mask bit written in bit 0 is copied intact to bit 2 and bit 3 is cleared. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. in reads of this register, the master dma reads the current mask value in bit 0. the legacy dma controllers single- channel mask register is write-only, therefore the multi- channel mask shadow register is read. it returns the mask bits for all four channels in the dma controller in such a way that the channel 0 mask is returned in bit 0, the channel 1 mask in bit 1, the channel 2 mask in bit 2, and the channel 3 mask in bit 3. the bit corresponding to the slave channel number is copied to bit 0 and the remaining bits are cleared. status register the master dma reads the current terminal count (tc) status value replicated four times in data bits 0C3 and the current channel request (drq) status value replicated four times in data bits 4C7. the legacy dma controllers status register returns the terminal count status and request bits for all four
functional operations 5-49 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information channels in the dma controller. the tc bit corresponding to the slave channel number is copied to bits 0C3, and the drq bit corresponding to the slave channel number is copied to bits 4C7. 5.10.5 dma software commands master clear the functionality of this register is identical to the legacy dma controller, so data is passed through unchanged. 5.10.6 dma addressing each legacy dma channel has two legacy addresses defined to store the base memory address and count information. located at these byte legacy addresses are 16-bit registers. the state of the first/last flip-flop determines which byte (high or low) is being accessed. the slave dma does not suffer this problem because it has fully decoded these registers. table 5-14 shows the relationship between legacy dma addressing for base, count, and memory page registers. it also shows where this information is programmed into the slave dma. for the byte legacy dma, bits 0C7 represent address 0C7. however, for the word legacy dma, bits 0C7 represent address 1C8. this carries forward to the next address byte. the memory page register re- aligns the bit position to the address. this relationship is maintained in the slave dma. a slave dma can be programmed to be in 8-bit/16-bit transfer mode from its pci configuration space. this mode information defines how the slave dma treats the data in the registers. table 5-14 also defines optional non-legacy addressing extensions for the slave.
5-50 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.10.7 pci slave dma configuration registers there must be one slave configuration register for each slave channel in a device, with bit 0 being the channel enable bit. the slave base address, along with a matching base address in the master dma indicates the dma channel to which the slave dma is mapped. no two slave dma channels can be programmed with the same slave base address, because bits 6C 4 of the base address are read-only values that equal the channel number. the slave dma is only required to support at least one transfer size. the first four slave dma channels only support 8-bit table 5-14. dma registers legacy channel base address base address memory page count address count address channel 0 0000h 0000h 0087h 0001h 0001h channel 1 0002h 0002h 0083h 0003h 0003h channel 2 0004h 0004h 0081h 0005h 0005h channel 3 0006h 0006h 0082h 0007h 0007h address 1 C 8 address 9 C 16 address 17 C 23 address 1 C 8 address 9 C 16 channel 4 00c0h 00c0h n/a 00c2h 00c2h channel 5 00c4h 00c4h 008bh 00c6h 00c6h channel 6 00c8h 00c8h 0089h 00cah 00cah channel 7 00cch 00cch 008ah 00ceh 00ceh above channels map to slave address base + 0h base + 1h base + 2h base + 4h base + 5h 8-bit mode address 0 C 7address 8 C 15 address 16 C 23 address 0 C 7 address 8 C 15 16-bit mode address 1 C 8address 8 C 16 address 17 C 23 address 1 C 8address 8 C 16 non-legacy slave dma addressing extensions base address base + 3h count address base + 6h 8-bit mode address 24 C 31 address 16 C 23 16-bit mode address 24 C 31 address 17 C 23 notes: 1. any slave dma that does not support the non-legacy extensions must always return a value of 00h from these locations when read. 2. it is the responsibility of the master dma to support the reserved memory page registers. because the AMD-645 peripheral bus controller implements subtractive decoding for these registers, master dma blocks that implement them will behave as expected by the distributed dma specification.
functional operations 5-51 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information transfers, so bits 2 and 1 always read 00b. the second four slave dma channels only support 16-bit transfers, so bits 2 and 1 always read 01b. no other transfer sizes are supported. non-legacy extended addressing is not supported. the dma slave channel accepts writes to bits 31C24 of the address register and bits 23C16 of the count register, with reads from those bits returning zeroes for data. 5.11 isa bus refresh cycle types the AMD-645 peripheral bus controller supports decoupled refresh mode only. the pc/at-compatible refresh period of 15.625 microseconds is supported by dividing the osc signal. the AMD-645 peripheral bus controller supports only off- board refresh timing. data in dram on the isa bus is refreshed every 15.64 microseconds. a refresh request can be generated by either the AMD-645 peripheral bus controller in pci bus master mode, or by an add-on card in isa master mode. the only difference between the refresh requests is that the requester drives the refresh# pin. the refresh address is put on sa[8:0] by the AMD-645 peripheral bus controller (regardless of which master currently owns the bus) in response to a low refresh# signal. the sa[16:9] addresses are three-stated. sa[19:17] are driven low. memr# is asserted by the AMD-645 peripheral bus controller one bclk cycle after refresh# goes active. memr# remains low for two bclk cycles. the refresh# signal is negated one bclk period after memr# negates.
5-52 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.12 fast ide/eide interface 5.12.1 ide drive registers the ide registers are 1f0h through 1f7h for the primary channel and 170h through 177h and 376h for the secondary channel. these registers are not resident in the AMD-645 peripheral bus controller, but are incorporated into the actual drive mechanism. the contents of the ide registers are relatively straightforward, but the legacy ata registers are detailed here for completeness. the address map for these registers is shown in table 5-15. table 5-15. ide register map channel 0 channel 1 type description 1f0h 170h read/write data register (16-bit) 1f1h 171h read-only write-only error register (8-bit) features register (8-bit) (former write compensation register) 1f2h 172h read/write sector count register (8-bit) 1f3h 173h read/write sector number register 1f4h 174h read/write low cylinder number register (8-bit) 1f5h 175h read/write high cylinder number register (8-bit) 1f6h 176h read/write drive/head register (8-bit) 1f7h 177h read-only write-only status register (8-bit) command register (8-bit) 3f6h 376h read-only write-only alternate status register (8-bit)contains the same information as the status register at offset 1f7h but does not clear the interrupt or imply interrupt acknowledge device control register (8-bit)bit 2 is the software reset bit. bit 1 is the enable bit for the drive interrupt to the host.
functional operations 5-53 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.12.2 pci cycles the ide controller supports 8-bit, 16-bit, and 32-bit pci cycles with the appropriate conversions to the 8-bit or 16-bit ide register, as shown in table 5-16. the ide data register is a 16- bit register located at 1f0h or 170h. the ide control registers are 8-bit registers located at 1f1hC1f7h and 3f6h, or at 171hC 177h and 376h. non-fifo ide writes when the cpu issues a write access to the ide, the command process issues the command to the i/o process. the i/o process then waits for the address setup time to satisfy the ior#/iow# precharge of the previous operation. iow# becomes active for the pre-set duration. fifo ide writes in fifo ide writes, the ide interface simply latches the data and decodes the address into the fifo. if the fifo is full, the ide interface waits until the fifo is empty due to the completion of one ide write transfer. the ide interface signals the pci slave to disconnect and retry the ide write. non-read-ahead ide reads read accesses to the ide interface must wait until the write- fifo is empty to ensure the proper execution order. if the write-fifo is not empty, the read access is retried at the pci interface and the write-fifo is flushed. when the write-fifo is empty, the ior# pre-charge and address setup time are satisfied and ior# becomes active for the programmed duration. accesses to the control registers are not buffered, and any access to these addresses will invalidate data in the read-ahead buffer. read-ahead ide reads read accesses to the ide interface must wait until the write- fifo is empty to ensure the proper execution order. if the table 5-16. pci cycles pci cycle ide register ide cycle comments byte data word the upper byte is always transferred byte control byte word data word word control 2 byte two sequential ide accesses are generated doubleword data 2 word two ide accesses to the data register are generated doubleword control 4 byte four sequential ide accesses are generated
5-54 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information write-fifo is not empty, the read access is retried at the pci interface and the write-fifo is flushed. when the write-fifo is empty, it issues the ior# command to the ide, as in the case of a non-read-ahead read transfer. if the read is not to the data register, the cycle behaves as if it is a normal non-read-ahead operation. if the read is to the data register, then the read-ahead cycle begins operating. the i/o process block issues the ior# to the ide until the read-ahead buffer is full, without cpu intervention. if the ide is slow enough to let the cpu catch up, the pci trdy# is returned after the ior#. in this case, read-ahead still helps since ior# starts before the cpu cycle. read-ahead is intended for data register reads. it counts the number of words to be transferred from the data register. however, there might be applications that transfer control data from the data port, which might not work with the prediction. the ide interface is designed to terminate the read-ahead cycle if it senses any of the following: n read or write accesses to ide control registers (any register other than the data register) n write access to the data register n read-ahead count expires (normal read-ahead termination) 5.12.3 dma bus mastering ide dma is supported through the pci-ide bus mastering logic. in a typical bus master command sequence, the bus master registers are initialized with the transfer address and count. next, the pci interface begins transfering long words to or from the fifo. the drive is then commanded to begin transfering words to or from the fifo using a drq/dack# handshake and ior# or iow# strobes. the transfer continues until the transfer count is exhausted or until the drive generates an interrupt. each ide channel has bidirectional fifo with a maximum of 64 bytes. only dma accesses are placed in this fifo. the direction of the fifo is controlled by registers. for pci bus mastering dma accesses, the bus master command and status registers determine the direction of the fifo. both channels cannot operate over the ide interface simultaneously due to
functional operations 5-55 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the 16-bit ide data bus shared between two channels. note, however, that a channels fifo may be connected to the pci data bus while the other channels fifo is connected to the ide data bus. to initiate a bus master transfer between memory and an ide dma slave device, the following steps are required: 1. software prepares a physical region descriptor (prd) table in system memory. each prd is 8 bytes long and consists of an address pointer to the starting address and the transfer count of the memory buffer to be transferred. in any given prd table, two consecutive prds are offset by eight bytes and are aligned on a 4-byte boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/write control bit. clear the interrupt bit and the error bit in the status register. 3. software issues the appropriate dma transfer command to the disk device. 4. engage the bus master function by writing a 1 to the start bit in the bus master ide command register for the appro- priate channel. 5. the controller transfers data to or from memory, respond- ing to dma requests from the ide device. 6. at the end of the transfer the ide device signals an inter- rupt. this interrupt is generated as isa interrupt 14 for the primary channel or as isa interrupt 15 for the secondary channel. 7. in response to the interrupt, software resets the start/stop bit in the master command register, then reads the control- ler status and drive status to determine whether the trans- fer completed successfully. the physical memory transfer region is described by a physical region descriptor (prd). the data transfer proceeds until all regions described by the prds in the table are transferred. each prd entry is eight bytes long. the first four bytes specify the byte address of a physical memory region. the next two bytes specify the count of the region in bytes, with a 64-kbyte
5-56 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information limit per region. a value of zero in these two bytes indicates 64 kbytes. bit 7 of the last byte indicates the end of the table. bus master operation terminates when the last descriptor has been retired. 5.12.4 ide channel arbitration the ide channel arbiter controls the ide data and address paths between the two ide channels. the arbiter must determine which channel already has access to the bus and what type of access is occurring. on dma accesses, the data bus is controlled and the address bus is not. for pio accesses, both the data and address buses are controlled. pio accesses the ide arbiter monitors the address decode logic of each channel to determine when there is an access. on access, the data and address buses will be steered to the channel where the access occurred. the pio access will be retried if the dma fifo is not empty, or if a dack# is active. the pio access causes a flush of the dma fifo if it is not empty. dma accesses the ide arbiter monitors the dma request from the drives. when the drq from a drive is detected, its channel receives the data bus. when the drq is de-asserted, the ide arbiter re- arbitrates for the ide data bus. if a dma access from a channel is in process during a pio request from the same channel, the pci bus access to the ide will end in a retry. if a dma access from a channel is in process during a pio request from the other channel, the dma grant is removed and the pci bus access to the ide ends in a retry with a delayed transaction implemented internally. the ide arbiter notifies the pci bus to retry the cycle. interrupt routing the interrupt from the ide drive is routed to the AMD-645 peripheral bus controller. two potential interrupt sources are made available to each ide channel. one is a plug-n-play (pnp) interrupt and the other is the isa irq input. the interrupt source is selected with the ide configuration register, function 1, offset 9h, such that isa compatibility mode or native pci mode can be selected. if the isa irq is selected, the interrupt routing register in function 0, offset 4ah can be used to select the ide interrupt source. the primary channel uses irq14 and can be set to irq15, irq10,
functional operations 5-57 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information or irq11, while the secondary channel uses irq15 and can be set to irq14, irq10, or irq11. if the isa irq is selected, the pnp irq has no effect on the ide irq output. if the pnp irq is selected, the ide interrupt output is anded with the isa irq. if the ide interrupt is disabled, the isa irq is passed through with no change. this configuration allows the option of interrupt sharing on the ide channels interrupt level. 5.12.5 ide configuration registers each ide channel has a complete and independent set of configuration registers. the registers for the primary channel and the secondary channel are identical except for their addresses in pci configuration space function 1. the primary channel registers are located at offset 10hC1bh. the secondary channel registers are located at offset 18hC1fh. figure 5-27. pio cycle t 2 t 3 t 4 t wds t wdh t 5 t rds t rdh pclk dcs3#/dcs1# da[2:0] diow# dd write dior# dd read
5-58 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 5-28. ide multiword dma cycle 5.13 power management support 5.13.1 power management subsystem the power management function of the AMD-645 peripheral bus controller is indicated in the following block diagram. t 4 t wds t wdh t 5 t rds t rdh pclk ddrq ddack# soe# sdir diow# dd write dior# dd read
functional operations 5-59 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.13.2 power plane management there are three power planes inside the AMD-645 peripheral bus controller. this scheme is optimal for systems with atx power supplies, although it also works using non-atx power supplies. the key feature of the atx power supply is the power plane control gp0 (global standby) timer pwrbtn# ri# smi arbiter sleep/wake state machine smi# sci# - legacy only event logic - acpi / legacy event logic - acpi only event logic - smi events - sci/smi events dec 0 1 cpu stpclk# control gp1 (device idle) timer user interface hardware events rtc sci_en - acpi / legacy generic control features - acpi / legacy fixed control features - wake-up events pm timer sci arbiter bus master gpio primary events usb resume
5-60 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information availability of two sets of power sources. the first set is always on unless turned off by the mechanical switch. only one voltage (5 v) is available for this set. the second set includes the normal 5 v and 12 v power supplies and is controlled by the input signal pwron as well as a mechanical switch. this set of voltages is available only when both the mechanical switch is on and the pwron signal is high. the power planes powered by the above two sets of supplies are referred to as v dd -5vsb and v dd , respectively. in addition to the two power planes, a third plane is powered by the combination of 5vsb and vbat for the integrated real time clock. most of the circuitry inside the AMD-645 peripheral bus controller is powered by v dd . very little logic is powered by v dd -5vsb and it remains functional as long as the mechanical switch of the power supply is turned on. the main function of this logic is to control the power supply of the v dd plane. general purpose i/o ports as acpi-compliant hardware, the AMD-645 peripheral bus controller includes pwrbtn# (pin 91) and ri# (pin 93) pins to implement power button and ring indicator functionality. in addition, a pwron pin (pin 107) is also available to control the v dd power plane by v dd -5vsb-powered logic. furthermore, the AMD-645 peripheral bus controller offers many general purpose i/o ports with the following capabilities: n i 2 c support n three gpio ports without external logic in addition to the i 2 c port. five gpio ports are available if i2c functionality is not used. every port can be used as inputs, outputs or i/o with external sci/smi capabilities. n sixteen gpi and sixteen gpo pins using external buffers (244 buffers for input and 373 latches for output) pins 87, 88, and 94 of the AMD-645 peripheral bus controller are dedicated general purpose i/o pins that can be used as inputs, outputs, or i/o with external smi capability. in particular, pins 87 and 88 can be used to implement a software- implemented i 2 c port for system configuration and general purpose peripheral communication. pins 92 and 136 can be configured either as dedicated general purpose i/o pins or as control signals for external buffers for implementing up to sixteen gpi and sixteen gpo ports. the gpi and gpo ports are connected to sd[15:8] and xd[7:0]. the configuration is
functional operations 5-61 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information determined in the gpio4_cfg and cpio3_cfg bits of the pin_cfg register. gpio4_cfg defaults to 1 to define pin 136 as gpio4. clear gpio4_cfg to redefine the pin as gpo_we latch enable. gpio3_cfg defaults to 1 to define pin 92 as gpio3. clear gpio3_cfg to redefine the pin as gpi_re# buffer enable. 5.13.3 power management events three types of power management events are supported: 1. acpi-required fixed events defined in the pm1a_sts and pm1a_en registers. these events can trigger the following sci or smi events depending on the sci_en bit: ? pwrbtn# triggering ? rtc alarm ? acpi power management timer carry (always sci) ? bios release (always sci) 2. acpi-aware general purpose function events defined in gp_sts and gp_sci_en, and gp_smi_en registers. these events can trigger the following sci or smi events depend- ing on the setting of individual smi and sci enable bits: ? extsmi triggering ? usb resume ? ri# indicator 3. generic global events defined in the gbl_sts and gbl_en registers. these registers are used primarily for the following smi events: ? gp0 and gp1 timer time out ? secondary event timer time out ? occurrence of primary events (defined in register pac t _ s ts a n d pac t _ e n ) ? legacy usb accesses (keyboard and mouse) once enabled, each of the extsmi inputs triggers an sci or smi at either the rising or falling transition of the corresponding input pin signal. software can check the status
5-62 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information of the input pins via register extsmi_val and take proper actions. among many possible actions, the sci and smi routine can change the processor state by programming the p_blk registers. the routine can also set the slp_en bit to put the system into one of the following two suspend states: 1. suspend to disk (or soft-off)the v dd power plane is turned off while v dd -5vsb and v dd -rtc planes remain on. 2. power-on-suspendall power planes remain on but the processor is put in the c3 state. in either suspend state, there is minimal interface between powered and non-powered planes. the AMD-645 peripheral bus controller allows the following events to wake up the system from the two suspend states and from the c2 state to the normal working state (processor in c0 state): n activation of external inputspwrbtn#, ri#, gpio0 and other extsmi pins (see table below) n rtc alarm and acpi power management timer(see table below) n usb resume event(see table 5-17) n interrupt eventsalways resume independent of any register setting n isa master or dma eventsalways resume independent of any register setting
functional operations 5-63 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the AMD-645 peripheral bus controller also provides flexible sci/smi steering and pwron control for the events listed in table 5-17. table 5-18 shows the availability of resume events in each type of suspend state. table 5-17. sci/smi/resume control for pm events event global sci/smi control individual enable bits for sci & smi separate control for pwron resume pwrbtn sci_en bit n y ri n y y rtc alarm n y n gp1o0 (extsmi0) n y y external sci/smi (non-gpio0) ny y acpi pm timer always sci n n usb resume n n y table 5-18. suspend resume events and conditions input trigger power plane soft-off power-on suspend pwrbtn# v dd -5vsb yes yes ri# v dd -5vsb yes yes rtc alarm vbat yes yes gp1o0 (extsmi0#) v dd -5vsb yes yes external sci/smi (non-gpio0) v dd -5v no yes acpi pm timer v dd -5v no yes usb resume v dd -5v no yes pci/isa interrupts v dd -5v no yes pci/isa master/dma v dd -5v no yes
5-64 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 5.13.4 legacy management timers in addition to the acpi power management timer, the AMD-645 peripheral bus controller includes the following four legacy power management timers: n gp0 timergeneral purpose timer with primary event n gp1 timergeneral purpose timer with peripheral event reload n secondary event timerto monitor secondary events n conserve mode timernot used in desktop applications the normal sequence of operations for a general purpose timer (gp0 or gp1) is as follows: 1. program the time base and timer value of the initial count (register gp_tim_cnt). 2. activate counting by setting the gp0_start or gp1_start bit to one: the timer will start with the initial count and count down towards 0. 3. when the timer counts down to zero, an smi will be gener- ated if enabled (gp0to_en and gp1to_en in the gbl_en register) with status recorded (gp0to_sts and gp1to_sts in the gbl_sts register). 4. each timer can also be programmed to reload the initial count and restart counting automatically after counting down to 0. this feature is not used in standard bios. the gp0 and gp1 timers can be used just as the general purpose timers described above. however, they can also be programmed to reload the initial count by system primary events or peripheral events thus used as the primary event (global standby) timer and peripheral timer, respectively. the secondary event timer is solely used to monitor secondary events.
functional operations 5-65 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 5.13.5 system primary and secondary events primary system events are distinguished in the pri_act_sts and pri_act_en registers. the bit controls in these registers are summarized in table 5-19. each category can be enabled as a primary event by setting the corresponding bit of the pri_act_en register. if enabled, the occurrence of the primary event reloads the gp0 timer if the pact_gp0_en bit is also set. the cause of the timer reload is recorded in the corresponding bit of the pri_act_sts register while the timer is reloaded. if no enabled primary event occurs during the count down, the gp0 timer will time out (count down to 0) and the system can be programmed (setting the gp0to_en bit in the gbl_en register to one) to trigger an smi to switch the system to a power down mode. the AMD-645 peripheral bus controller distinguishes two kinds of power management interrupt requests, primary and secondary interrupts. like other primary events, the occurrence of a primary interrupt demands that the system be restored to full processing capability. secondary interrupts are typically used for background housekeeping tasks that are unnoticeable to the user. the AMD-645 peripheral bus controller allows each channel of interrupt request to be table 5-19. pri_act_sts and pri_act_en register bits bit event trigger 7 keyboard access i/o port 60h 6 serial port access i /o ports 3f8h-3ffh, 2f8h-2ffh, 3e8h-3efh, or 2e8h-2efh 5 parallel port access i/o ports 378h-37fh or 278h- 27fh 4video access i/o ports 3b0h-3dfh or memory a/b segments 3 ide/floppy access i/o ports 1f0h-1f7h, 170h-177h, or 3f5h 2 reserved 1 primary interrupts each channel of the interrupt controller can be programmed as a primary or secondary interrupt 0 isa master/dma activity
5-66 functional operations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information declared as either primary, secondary, or ignorable in the pirq_ch and sirq_ch registers. secondary interrupts are the only system secondary events defined in the AMD-645 peripheral bus controller. like primary events, primary interrupts can be made to reload the gp0 timer by setting the pirq_en bit to 1. secondary interrupts do not reload the gp0 timer. therefore, the gp0 timer will time out and the smi routine can put the system into power down mode if no events other than secondary interrupts occur periodically in the background. primary events can be programmed to trigger an smi (setting of the pact_en bit). typically, this smi triggering is turned off during normal system operation to avoid degrading system performance. triggering is turned on by the smi routine before entering the power down mode so that the system may be returned to normal operation at the occurrence of primary events. at the same time, the gp0 timer is reloaded and the count down process is restarted. 5.13.6 peripheral events primary and secondary events define system events in general, and the response is typically expressed in terms of system events. individual peripheral events can also be monitored by the AMD-645 peripheral bus controller through the gp1 timer. the following four categories of peripheral events are distinguished (via register gp_rld_en): n bit 7keyboard access n bit 6serial port access n bit 4video access n bit 3ide/floppy access the four categories are subsets of the primary events as defined in pri_act_en, and the occurrence of these events can be checked through a common register pri_act_sts. as a peripheral timer, gp1 can be used to monitor one (or more than one) of the above four device types by programming the corresponding bit to one and the other bits to zero. timeout of the gp1 timer indicates no activity of the corresponding device type and appropriate action can be taken as a result.
initialization 6-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 6 initialization all programmable features in the AMD-645 peripheral bus controller are controlled by the pci configuration registers, which are normally programmed only during system initialization. this chapter summarizes the register functions, default values, access types, and addresses. for more detailed descriptions of the configuration registers, see section 7. access types are indicated as follows: rw read/write ro read only wo write only rwc read, write 1s to clear individual bits 6.1 legacy i/o registers table 6-1. master dma controller registers port register name access 00h ch 0 base/current address rw 01h ch 0 base/current count rw 02h ch 1 base/current address rw 03h ch 1 base/current count rw 04h ch 2 base/current address rw 05h ch 2 base/current count rw 06h ch 3 base/current address rw 07h ch 3 base/current count rw 08h status/command rw 09h write request wo 0ah write single mask wo 0bh write mode wo 0ch clear byte pointer f/f wo 0dh master clear wo 0eh clear mask wo 0fh r/w all mask bits rw
6-2 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 6-2. master interrupt controller registers port register name access 20h master interrupt control note 1 21h master interrupt mask note 1 20h master interrupt control shadow rw 21h master interrupt mask shadow rw note: 1. rw if shadow registers are disabled table 6-3. timer/counter registers port register name access 40h timer/counter 0 rw 41h timer/counter 1 rw 42h timer/counter 2 rw 43h timer/counter control wo table 6-4. keyboard controller registers port register name access 60h keyboard controller data rw 61h misc. functions and speaker control rw 64h keyboard controller command/status rw table 6-5. cmos/rtc/nni registers port register name access 70h cmos memory address & nmi disable wo 71h cmos memory data (128 bytes) rw 72h cmos memory address rw 73h cmos memory data (256 bytes) rw 74h cmos memory address rw 75h cmos memory data (256 bytes) rw
initialization 6-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 6-6. dma page registers port register name access 87h dma pagedma channel 0 rw 83h dma pagedma channel 1 rw 81h dma pagedma channel 2 rw 82h dma pagedma channel 3 rw 8fh dma pagedma channel 4 rw 8bh dma pagedma channel 5 rw 89h dma pagedma channel 6 rw 8ah dma pagedma channel 7 rw table 6-7. system control registers port register name access 92h system control rw table 6-8. slave interrupt controller registers port register name access a0h slave interrupt control note 1 a1h slave interrupt mask note 1 a0h slave interrupt control shadow rw a1h slave interrupt mask shadow rw note: 1. rw if shadow registers are disabled
6-4 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 6-9. slave dma controller registers port register name access c0h ch 0 base/current address rw c2h ch 0 base/current count rw c4h ch 1 base/current address rw c6h ch 1 base/current count rw c8h ch 2 base/current address rw cah ch 2 base/current count rw cch ch 3 base/current address rw ceh ch 3 base/current count rw d0h status/command rw d2h write request wo d4h write single mask wo d6h write mode wo d8h clear byte pointer f/f wo dah master clear wo dch clear mask wo deh r/w all mask bits rw
initialization 6-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 6.2 pci function 0 registerspci-to-isa bridge table 6-10. configuration space pci-to-isa header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 0586h ro 05hC04h command 000fh rw 07hC06h status 0200h rwc 08h revision id (00h = first silicon) ro 09h program interface 00h ro 0ah sub class code 01h ro 0bh base class code 06h ro 0ch reserved (cache line size) 00h 0dh reserved (latency timer) 00h 0eh header type 80h ro 0fh built-in self test (bist) 00h ro 10hC3fh reserved 00h
6-6 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 6-11. isa bus control registers offset register default recommended access setting result 40h isa bus control 00h 00h normal isa timing rw 41h isa test mode 00h 01h refresh test mode rw 42h isa clock control 00h 00h isa clock=pciclk/4 rw 43h rom decode control 00h 00h romcs# f0000h-f ffffh rw 44h keyboard controller control 00h 01h disable mouse lock rw 45h type f dma control 00h 00h set dma type f if needed rw 46h miscellaneous control 1 00h 10h disable post memory write rw 47h miscellaneous control 2 00h c0h init as cpu reset enable pci delay transaction rw 48h miscellaneous control 3 01h 01h enable usb, ide rw 49h reserved 00h 00h 4ah ide interrupt routing 04h c4h wait for pgnt before grant to isa master/dma access ports 00-ffh via sd ide primary channel irq14 secondary channel irq 15 rw 4bh reserved 00h 00h 4ch dma/master mem access ctrl 1 00h 00h pci memory hole bottom address ha23Cha16 = 0 rw 4dh dma/master mem access ctrl 2 00h 00h pci memory hole top address ha23Cha16 = 0 rw 4fhC4eh dma/master mem access ctrl 3 0300h f300h top of pci memory for isa=16m. forward 00000h-9 ffffh access to pci rw
initialization 6-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 6-12. plug-n-play control registers offset register default recommended access setting result 50h reserved (do not program) 24h 24h rw 53hC51h reserved 00h 00h 54h pic irq edge/level selection 00h 00h pirqs inverted edge trigger/ non-inverted level trigger rw 55h pnp routing for external mirq0C1 00h 00h mirqs disabled rw 56h pnp routing for pci intbCa 00h b0h intb routes to irq11 inta disabled rw 57h pnp routing for pic intdCc 00h 57h intd routes to irq5 intc routes to irq7 rw 58h pnp routing for external mirq2 00h 00h mirq2 disabled rw 59h mirq pin configuration 04h 04h configure as master# rw 5ah xd power-on strap options note 1 f7h enable int rtc, ps2 mouse, int kbc rw 5bh internal rtc test mode 00h 00h rtc reset enable, sram access enable, test enable rw 5chC5fh reserved 00h 00h notes: power-up default value depends on external strapping table 6-13. distributed dma offset register default recommended access setting result 61hC60h channel 0 base address/enable 0000h 0000h disabled rw 63hC62h channel 1base address/enable 0000h 0000h disabled rw 65hC64h channel 2 base address/enable 0000h 0000h disabled rw 67hC66h channel 3 base address/enable 0000h 0000h disabled rw 69hC68h reserved 0000h 0000h disabled 6bhC6ah channel 5 base address/enable 0000h 0000h disabled rw 6dhC6ch channel 6 base address/enable 0000h 0000h disabled rw 6fhC6eh channel 7 base address/enable 0000h 0000h disabled rw 70hCffh reserved 00h 00h
6-8 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 6.3 pci function 1 registerside control table 6-14. configuration space ide header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 0571h ro 05hC04h command 0080h rw 07hC06h status 0280h rw 08h revision id (00h = first silicon) ro 09h program interface 8ah rw 0ah sub class code 01h ro 0bh base class code 01h ro 0ch reserved (cache line size) 00h 0dh latency timer 20h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 13hC10h base addressprimary data/command 0000_01f0h rw 17hC14h base addressprimary control/status 0000_03f4h rw 1bhC18h base addresssecondary data/command 0000_0170h rw 1fhC1ch base addresssecondary control/status 0000_0374h rw 23hC20h base addressbus master control 0000c_c01h rw 24hC2fh reserved (unassigned) 00h 30hC33h reserved (expansion rom base address) 00h 34hC3ch reserved (unassigned) 00h 3ch interrupt lines 0eh rw 3dh interrupt pin 00h ro 3eh minimum grant 00h ro 3fh maximum latency 00h ro
initialization 6-9 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 6-15. configuration space ide registers offset register default recommended access setting result 40h chip enable 04h 0bh enable pri and sec channel rw 41h ide configuration 02h e2h enable pri and sec read prefetch buffer enable pri post write buffer rw 42h reserved (do not program) 09h 09h rw 43h fifo configuration 3ah 3ah allocate 8 word buffers in both pri and sec channel set threshold to 1/2 rw 44h miscellaneous control 1 68h 68h master read/write cycle irdy# 1 wait state fifo output data 12 clock advance rw 45h miscellaneous control 2 00h 00h no channel interrupts swap rw 46h miscellaneous control 3 c0h c0h pri and sec ch read dma fifo flush enabled no limit in drdy pulse width rw 4bhC48h drive timing control a8a8a8a8h a8a8a8a8h dior# and diow# pulse width set to 11 pci clocks recovery time set to 9 clocks rw 4ch address setup time ffh ffh address setup time 4t rw 4dh reserved (do not program) 00h 00h rw 4eh sec non-1f0h port access timing ffh ffh sec non-1f0 port access, dior# and diow# pulse width set to 17 pci clocks rw 4fh pri non-1f0h port access timing ffh ffh pri non-1f0 port access, dior# and diow# pulse width set to 17 pci clocks rw 53hC50h ultradma33 extd timing control 03030303h 03030303h pri and sec drive 0 and 1mode enabled by set feature command disabled ultradma33-mode rw 57h-54h reserved 00h 00h 5fhC58h reserved a8a8a8a8h a8a8a8a8h 61hC60h primary sector size 0200h 0200h 200h bytes per sector rw 67hC62h reserved 00h 00h 69hC68h secondary sector size 0200h 0200 200h bytes per sector rw 6ahCffh reserved 00h 00
6-10 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 6.4 pci function 2 registersusb controller table 6-16. ide controller i/o registers offset register name default access 00h primary channel command 00h rw 01h reserved 00h 02h primary channel status 00h rwc 03h reserved 00h 07hC04h primary channel prd table address 00h rw 08h secondary channel command 00h rw 09h reserved 00h 0ah secondary channel status 00h rwc 0bh reserved 00h 0fhC0ch secondary channel prd table address 00h rw table 6-17. configuration space usb header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 3038h ro 05hC04h command 0000h rw 07hC06h status 0200h rwc 08h revision id (00h = first silicon) ro 09h program interface 00h ro 0ah sub class code 03h ro 0bh base class code 0ch ro 0ch reserved (cache line size) 00h ro 0dh latency timer 16h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 10hC1fh reserved 00h 23hC20h base address 0000301h rw 24hC3bh reserved 00h 3ch interrupt line 00h rw 3dh interrupt pin 04h rw 3ehC3fh reserved 00h
initialization 6-11 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 6-18. configuration space usb registers offset register default recommended access setting result 40h miscellaneous control 1 00h 00h support mrl, mrm, mwi isb data length 1280 disable usb power management dma 16 dw burst access pci zero wait state rw 41h miscellaneous control 1 00h 00h always set trap 60/64 status bit a20gate pass through rw 42hC43h reserved 00h 00h ro 44hC46h reserved (do not program) 00c2h 00c2h rw 47h reserved 0ch 0ch 48hC5fh reserved 00h 00h 60h serial bus release number 10h 10h always read 10h ro 61hCbfh reserved 00h 00h c1hCc0h legacy support 2000h 2000h always read 2000h ro c2hCffh reserved 00h 00h table 6-19. usb controller i/o registers offset register name default access 01hC00h usb command 0000h rw 03hC02h usb status 0000h rwc 05hC04h usb interrupt enable 0000h rw 07hC06h frame number 0000h rw 0bhC08h frame list base address 00000000h rw 0ch start of frame modify 40h rw 11hC10h port 1 status/control 0080h rwc 13hC12h port 2 status/control 0080h rwc
6-12 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 6.5 pci function 3 registerspower management 6.5.1 power management configuration space registers table 6-20. configuration space power management header registers offset pci header default access 01hC00h vendor id 1106h ro 03hC02h device id 3040h ro 05hC04h command 0000h rw 07hC06h status 0280h rwc 08h revision id (00h = first silicon) ro 09h program interface 00h ro 0ah sub class code 00h ro 0bh base class code 00h ro 0ch reserved 00h ro 0dh latency timer 16h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 10hC1fh reserved 00h 23hC20h i/o register base address 00000001h rw 24hC3fh reserved 00h
initialization 6-13 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 6.5.2 power management i/o space registers table 6-21. configuration space power management registers offset register default recommended access setting result 40h pin configuration c0h c0h define pin 136 as gpio4 define pin 92 as gpio4 rw 41h general configuration 00h 00h disable pwrbtn# debounce disable acpi timer reset acpi 24-bit timer count 32us clock throttling rw 42h sci interrupt configuration 00h 00h disable sci interrupt rw 43h reserved 00h 00h rw 45hC44h primary interrupt channel 0000h 0000h disable pri interrupt channel rw 47hC46h secondary interrupt channel 0000h 0000h disable sec interrupt channel rw 53hC50h gp timer control 00000000h 00000000h disable conserve mode disable sec event time disable gp1 timer disable gp0 timer rw 54hC60h reserved 00h 00h 61h programming interface read value 00h 00h value to be returned by register at offset 09h wo 62h sub class read value 00h 00h value to be returned by register at offset 0ah wo 63h base class read value 00h 00h value to be returned by register at offset 0bh wo 64hCffh reserved 00h 00h table 6-22. basic power management control/status registers offset register name default access 01hC00h power management status 00h rwc 03hC02h power management enable 00h rw 05hC04h power management control 00h rw 0bhC08h power management timer 00h rw
6-14 initialization AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 6-23. processor power management registers offset register name default access 13hC10h processor control 0000h rw 14h processor level 2 00h ro 15h processor level 3 00h ro table 6-24. general purpose power management registers offset register name default access 21hC20h general purpose status 00h rwc 23hC22h general purpose sci enable 00h rw 25hC24h general purpose smi enable 00h rw 27hC26h power supply control 00h rw table 6-25. generic power management registers offset register name default access 29hC28h global status 00h rwc 2bhC2ah global enable 00h rw 2dhC2ch global control 00h rw 2fh smi command 00h rw 33hC30h primary activity detect status 00h rwc 37hC34h primary activity detect enable 00h rw 3bhC38h gp timer reload enable 00h rw table 6-26. general purpose i/o offset register name default access 40h gpio direction control 00h rw 42h gpio port output value 00 rw 44h gpio port input value input ro 47hC46h gpo port output value 0000 rw 49hC48h gpi port input value input ro
registers 7-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7 registers this section summarizes the AMD-645 peripheral bus controller configuration and i/o registers. where applicable, they also document the power-on default value and access type for each register. access type definitions are as follows: n rw (read/write) n ro (read only) n wo (write only) n reserved n rwc (read, write 1s to clear individual bits) registers indicated as rw may have some read-only bits that always read back a fixed value (usually 0 if unused). registers designated as rwc may have some read-only or read-write bits (see individual register descriptions for details). 7.1 pci mechanism #1 the AMD-645 peripheral bus controller uses pci configuration mechanism #1 to convey and receive configuration data to and from the host processor. this mechanism, described in pci local bus specification revision 2.1 , employs i/o locations 0cf8h to 0cfbh to specify the target address and locations 0cfch to 0cffh for data to the target address. the target address includes the specific pci bus, device, function number, and register number within a pci device. configuration address is a read-write port that responds only to doubleword accesses. byte or word accesses are passed on unchanged. configuration address ports 0cfbhC0cf8h 31 bit 30 C bit 24 bit 23 C bit 16 bit 15 C bit 11 10 C 8 bit 7 C bit 2 1 0 en reserved bus number device number function # register number 0 0 i/o address ocfbh i/o address ocfah i/o address ocf9h i/o address ocf8h
7-2 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 31 configuration space enable 1 = the targeted pci device responds. 0 = the i/o access is passed on unchanged. bits 30C24 reserved (always reads 0) bits 23C16 pci bus number these bits are used to choose a specific system pci bus. bits 15C11 device number these bits are used to choose a specific system device. bits 10C8 function number these bits are used to choose the number of a specific function space in memory. bits 7C2 register number these bits are used to specify the offset number of a register within the chosen function space. the register number is a doubleword which, in conjunction with the pci byte enable lines c/be3C c/be0#, specifies the configuration register offset number. bits 1C0 fixed (always reads 0) configuration data is a read-write port that responds only to doubleword accesses. byte or word accesses will be passed on unchanged. 7.2 legacy i/o registers this group of i/o registers includes keyboard and mouse control, dma controllers, interrupt controllers, and timer/counters, as well as a number of miscellaneous ports originally implemented using discrete logic on the original pc/at. these registers are implemented in a precise manner for backwards compatibility with previous generations of pc hardware. these registers are listed for reference only. detailed descriptions of the actions and programming of these registers are included in other industry publications. all of the registers reside in i/o space. they are grouped according to their AMD-645 peripheral bus controller functions. the i/o port address and access type are given for each register. configuration data ports 0cfchC0cffh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxxb
registers 7-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7.2.1 keyboard controller registers the keyboard controller handles the keyboard and mouse interfaces using port 60h and port 64h. reads from port 64h return a status byte. writes to port 64h are command codes. data is transferred via port 60h. bit 7 parity error 1 = a parity error occurred on the last byte received from keyboard/mouse 0 = no parity error (odd parity received = default) bit 6 general receive/transmit timeout 1=error 0 = no error (default) bit 5 mouse output buffer full 1 = mouse output buffer full 0 = mouse output buffer empty (default) bit 4 keylock status 1=free 0 = locked (default) bit 3 command/data 1 = last write was command write 0 = last write was data write (default) bit 2 system flag 1 = self test successful 0 = power-on (default) bit 1 input buffer full 1 = keyboard input buffer full 0 = keyboard input buffer empty (default) bit 0 keyboard output buffer full 1 = keyboard output buffer full 0 = keyboard output buffer empty (default) keyboard/mouse status port 64h ro bit 7654321bit 0 bit name pe grt mob ks cd sf ib kob reset00000000
7-4 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information port 64hkeyboard/mouse commandis a write-only i/o register. this register, when written, is used to send commands to the keyboard/mouse controller. keyboard/mouse command codes recognized by the AMD-645 peripheral bus controller are listed in table 7-1. note that the keyboard controller is compatible with industry-standard 82c42 keyboard controllers except that, because of its integration into a larger chip, many of the i/o port pins are not available for external use as general-purpose i/o pins, even if p13Cp16 are set during power-up as strapping options. that is, many of the commands that follow are provided and work, but otherwise perform no useful function (e.g., commands that set p12Cp17 high or low). also note that setting p10C11, p22C23, p26C27, and t0C1 high or low serve no useful purpose because these bits are used to implement the keyboard and mouse ports and are directly controlled by keyboard controller logic. . keyboard/mouse command port 64h wo bit 7654321bit 0 bit name value of specific keyboard command (see table 10-1) reset00000000 table 7-1. keyboard controller command codes command code keyboard command code description 20h read control byte (next byte is control byte) 60h write control byte (next byte is control byte) 9xh write low nibble (bits 0C3) to input ports p10Cp13 a1h output keyboard controller version # a4h test if password is installed (returns f1h to indicate not installed) a7h disable mouse interface a8h enable mouse interface a9h mouse interface test (results in port 60h) 0 = ok, 1 = clock stuck low, 2 = clock stuck high, 3 = data stuck low, 4 = data stuck high, ff = general error aah kbc self test (55h = ok, fch = not ok) abh keyboard interface test (results in port 60h) 0 = ok, 1 = clock stuck low, 2 = clock stuck high, 3 = data stuck low, 4 = data stuck high, ff = general error adh disable keyboard interface aeh enable keyboard interface afh return version # c0h read input port (read ports p10Cp17 input data to the output buffer) c1h poll input port low (read input data on input ports p11Cp13 repeatedly and put results in bits 5C7 of status register) c2h poll input port high (read input data on input ports p15Cp17 repeatedly and put results in bits 5C7 of status register)
registers 7-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information this register is accessible by writing commands 20h/60h to the command port (64h). the control byte is written by first sending a value of 60h to the command port, then sending the control byte value to 64h. the control register can be read by sending a command of 20h to port 64h, waiting for an output buffer full status reading on bit 5 or bit 0 of 64h, then reading the control byte value from port 60h. bit 7 reserved (always reads 0) bit 6 pc compatibility 1 = convert scan codes to pc format. convert 2-byte break sequences to 1- byte pc-compatible break codes (default) 0 = disable scan conversion bit 5 mouse disable 1 = disable mouse interface 0 = enable mouse interface (default) bit 4 keyboard disable 1 = disable keyboard interface 0 = enable keyboard interface (default) bit 3 keyboard lock disable 1 = disable keyboard inhibit function 0 = enable keyboard inhibit function (default) c8h unblock p22Cp23 (use before command d1 to change the active mode) c9h reblock p22Cp23 (protection mechanism for d1 command) cah read mode (output kbc mode info to port 60 output buffer) bit 0 = 0 = isa, bit 0 = 1 = ps/2 d0h read output port (copy p10Cp17 output values to port 60h) d1h write output port (data byte following is written to keyboard output port as if it came from the keyboard) d2h write keyboard output buffer & clear status bit 5 (write following byte to keyboard) d3h write mouse output buffer & set status bit 5 (write the following byte to the mouse, and put the value in mouse input buffer so it appears to have come from the mouse) d4h write mouse (write the following byte to the mouse) e0h read test inputs (t0Ct1 read to bits 0C1 of respective byte) exh set input ports p23Cp21 per command bits 3C1 fxh pulse input ports p23Cp20 low for 6 sec per command bits 3C0 note: codes not listed are undefined or their functions are eliminated by direct control of the keyboard controller logic. kbc control register port 60h or 64h rw bit 7654321bit 0 bit name reserved pcc md kd kld flag mie kie reset01000000 table 7-1. keyboard controller command codes (continued) command code keyboard command code description
7-6 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 2 system flag (this bit can be read back as [status register] port 64h bit 2) bit 1 mouse interrupt enable 1 = generate interrupt on irq12 when mouse output buffer has been written 0 = disable mouse interrupts (default) bit 0 keyboard interrupt enable 1 = generate interrupt on irq1 when keyboard output buffer has been written 0 = keyboard output buffer empty (default) traditional keyboard controllers traditional (non-integrated) keyboard controllers have an input port and an output port with specific pins dedicated to certain functions and other pins available for general purpose i/o. specific commands are provided to set these pins high and low. all outputs are open-collector to allow the pins to function as inputs. the output value for that pin is set high (non- driving), and the desired input value is read on the input port. these ports are defined as shown in table 7-2. table 7-2. traditional port pin definition bit input port locode hicode 0 p10 - keyboard data in b0 b8 1 p11 - mouse data in b1 b9 2 p12 - turbo pin (ps/2 mode only) b2 ba 3 p13 - user defined b3 bb 4 p14 - user defined b6 be 5 p15 - user defined b7 bf 6 p16 - user defined - - 7 p17 - undefined - - bit output port locode hicode 0 p20 - sysrst (1 = execute reset) - 1 p21 - gatea20 (1 = a20 enabled) - 2 p22 - mouse data out b4 bc 3 p23 - mouse clock out b5 bd 4 p24 - keyboard obf interrupt (irq1) - - 5 p25 - mouse obf interrupt (irq12) - - 6 p26 - keyboard clock out - - 7 p27 - keyboard data out - - bit test port locode hicode 0 t0 - keyboard clock in - - 1 t1 - mouse clock in - -
registers 7-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information this register should only be written when port 64h, bit 1 is 0. a value of 1 indicates that the input buffer is full. this register should only be read when port 64h, bit 0 is 1. a value of 0 indicates that the output buffer is empty. keyboard controller input buffer port 60h wo bit 7654321bit 0 bit name input buffer reset00000000 keyboard controller output buffer port 60h ro bit 7654321bit 0 bit name output buffer reset00000000
7-8 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 7.2.2 dma controller i/o registers master dma controller ports 00hC0fh channels 0C3 of the master dma controller control system dma channels 0C3. there are 16 master dma controller registers, as shown in table 7-3. table 7-3. ports 00hC0fh master dma controller i/o address bits 15C0 register name 0000 0000 000x 0000 ch 0 base/current address rw 0000 0000 000x 0001 ch 0 base/current count rw 0000 0000 000x 0010 ch 1 base/current address rw 0000 0000 000x 0011 ch 1 base/current count rw 0000 0000 000x 0100 ch 2 base/current address rw 0000 0000 000x 0101 ch 2 base/current count rw 0000 0000 000x 0110 ch 3 base/current address rw 0000 0000 000x 0111 ch 3 base/current count rw 0000 0000 000x 1000 status/command rw 0000 0000 000x 1001 write request wo 0000 0000 000x 1010 write single mask wo 0000 0000 000x 1011 write mode wo 0000 0000 000x 1100 clear byte pointer f/f wo 0000 0000 000x 1101 master clear wo 0000 0000 000x 1110 clear mask wo 0000 0000 000x 1111 r/w all mask bits rw note: not all address bits are decoded.
registers 7-9 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information slave dma controller ports c0hCdfh channels 0C3 of the slave dma controller control system dma channels 0C3. there are 16 slave dma controller registers, as shown in table 7-4. dma page registers ports 80hC8fh there are eight dma page registers, one for each dma channel. these registers provide bits 16C23 of the 24-bit address for each dma channel. bits 0C15 are stored in registers in the master and slave dma controllers. the dma page registers are located at the i/o port addresses shown in table 7-5. table 7-4. ports c0hCdfh slave dma controller i/o address bits 15C0 register name 0000 0000 1100 000x ch 0 base/current address rw 0000 0000 1100 001x ch 0 base/current count rw 0000 0000 1100 010x ch 1 base/current address rw 0000 0000 1100 011x ch 1 base/current count rw 0000 0000 1100 100x ch 2 base/current address rw 0000 0000 1100 101x ch 2 base/current count rw 0000 0000 1100 110x ch 3 base/current address rw 0000 0000 1100 111x ch 3 base/current count rw 0000 0000 1101 000x status/command rw 0000 0000 1101 001x write request wo 0000 0000 1101 010x write single mask wo 0000 0000 1101 011x write mode wo 0000 0000 1101 100x clear byte pointer f/f wo 0000 0000 1101 101x master clear wo 0000 0000 1101 110x clear mask wo 0000 0000 1101 111x r/w all mask bits rw note: not all address bits are decoded. table 7-5. ports 80hC8fh dma page registers i/o address bits 15C0 register name 0000 0000 1000 0111 ch 0 dma page (mC0) rw 0000 0000 1000 0011 ch 1 dma page (mC1) rw 0000 0000 1000 0001 ch 2 dma page (mC2) rw 0000 0000 1000 0010 ch 3 dma page (mC3) rw 0000 0000 1000 1111 ch 4 dma page (mC4) rw 0000 0000 1000 1011 ch 5 dma page (mC5) rw 0000 0000 1000 1001 ch 6 dma page (mC6) rw 0000 0000 1000 1010 ch 7 dma page (mC7) rw
7-10 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 7.2.3 interrupt controller registers master interrupt controller ports 20hC21h the master interrupt controller controls system interrupt channels 0C7. the two registers are shown in table 7-6. slave interrupt controller ports a0hCa1h the slave interrupt controller controls system interrupt channels 8C15. the slave system interrupt controller also occupies two register locations, as shown in table 7-7. 7.2.4 interrupt controller shadow registers the following shadow registers are enabled by setting bit 4 of offset 47h to 1. if the shadow registers are enabled, they are read back at the indicated i/o ports instead of the standard interrupt controller registers. writes to the standard ports are directed to the standard interrupt controller registers. table 7-6. ports 20hC21h master interrupt controller registers i/o address bits 15C0 register name 0000 0000 001x xxx0 master interrupt control rw 0000 0000 001x xxx1 master interrupt mask rw note: not all address bits are decoded. table 7-7. ports a0hCa1h slave interrupt controller registers i/o address bits 15C0 register name 0000 0000 101x xxx0 slave interrupt control rw 0000 0000 101x xxx1 slave interrupt mask rw note: not all address bits are decoded.
registers 7-11 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bits 7C5 reserved (always reads 0) bit 4 ocw3 bit 5 bit 3 ocw2 bit 7 bit 2 icw4 bit 4 bit 1 icw4 bit 1 bit 0 icw1 bit 3 bits 7C5 reserved (always reads 0) bits 4C0 t7Ct3 of the interrupt vector address bits 7C5 reserved (always reads 0) bit 4 ocw3 bit 5 bit 3 ocw2 bit 7 bit 2 icw4 bit 4 bit 1 icw4 bit 1 bit 0 icw1 bit 3 bits 7C5 reserved (always reads 0) bits 4C0 t7Ct3 of the interrupt vector address master interrupt control shadow port 20h ro bit 7654321bit 0 bit name reserved ocw3C5 ocw2C7 icw4C4 icw4C1 icw1C3 reset 0 0 0 xxxxxb master interrupt mask shadow port 21h ro bit 7654321bit 0 bit name reserved t7Ct3 of the interrupt vector address reset 0 0 0 xb xb xb xb xb slave interrupt control shadow port a0h ro bit 7654321bit 0 bit name reserved ocw3C5 ocw2C7 icw4C4 icw4C1 icw1C3 reset 0 0 0 xb xb xb xb xb slave interrupt mask shadow port a1h ro bit 7654321bit 0 bit name reserved t7Ct3 of the interrupt vector address reset 0 0 0 xxxxxb
7-12 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 7.2.5 timer/counter registers timer/counter registers ports 40hC43h there are four timer/counter registers, as shown in table 7-8. 7.2.6 cmos/rtc registers the system real-time clock (rtc) is part of the cmos block. the rtc control registers are located at specific offsets in the cmos data area (00hC0dh and 7dhC7fh). detailed descriptions of cmos/rtc operation and programming can be obtained from several industry publications. for reference, the definition of the rtc register locations and bits are summarized in table 7-9. table 7-8. ports 40hC43h timer/counter registers i/o address bits 15C0 register name 0000 0000 010x xx00 timer/counter 0 count rw 0000 0000 010x xx01 timer/counter 1 count rw 0000 0000 010x xx10 timer/counter 2 count rw 0000 0000 010x xx11 timer/counter command mode wo note: not all address bits are decoded.
registers 7-13 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 7-9. cmos register summary offset description binary range bcd range 00h seconds 00hC3bh 00hC59h 01h seconds alarm 00hC3bh 00hC59h 02h minutes 00hC3bh 00hC59h 03h minutes alarm 00hC3bh 00hC59h o4h hours am 12 hr: 01hC1ch 01hC12h pm 12 hr: 81hC8ch 81hC92h 24 hr: 00hC17h 00hC23h 05h hours alarmam 12 hr: 01hC1ch 01hC12h hours pm 12 hr: 81hC8ch 81hC92h hours 24 hr: 00hC17h 00hC23h 06h day of the weeksunday = 1: 01hC07h 01hC07h 07h day of the month 01hC1fh 01hC31h 08h month 01hC0ch 01hC12h 09h year 00hC63h 00hC99h 0ah bit 7 update in progress bits 6 C 4 divide (010 = enable oscillator and keep time) bits 3 C 0 rate select for periodic interrupt 0bh bit 7 inhibit update transfers bit 6 periodic interrupt enable bit 5 alarm interrupt enable bit 4 update ended interrupt enable bit 3 no function bit 2 data mode (0 = bcd, 1 = binary) bit 1 hours format (0 = 12, 1 = 24) bit 0 daylight saving enable 0ch bit 7 interrupt request flag bit 6 periodic interrupt flag bit 5 alarm interrupt flag bit 4 update ended flag bits 3 C 0 unused (always reads 0) 0dh bit 7 vrt (= 1 if vbat voltage is ok) bits 6 C 0 unused (always reads 0) 0ehC7ch software-defined storage registers (111 bytes) 7dh date alarm 01hC0fh 01hC31h 7eh month alarm 01hC0ch 01hC12h 7fh century field 13hC14h 19hC20h 80hCffh software-defined storage registers (128 bytes)
7-14 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information ports 70hC71h are compatible with pc industry standards and can be used to access the lower 128 bytes of the 256-byte on- chip cmos ram. ports 72hC73h can be used to access the full extended 256-byte space. these ports can be accessed only if function 0, offset 5ah, bit 2 is set to select the internal rtc. if this bit is cleared, accesses to port 70hC71h or 72hC73h will be directed to an external rtc. ports 74hC75h can be used to access the full on-chip extended 256-byte space when the on-chip rtc is disabled. these ports can be accessed only if function 0, offset 5bh, bit 1 is set to enable the internal rtc sram and if offset 48h, bit 3 is cleared to enable access to port 74hC75h. bit 7 nmi disable 1 = disable nmi generation (default) 0 = enable nmi generation. nmi is asserted on encountering iochck# on the isa bus or serr# on the pci bus. bits 6C0 cmos address (128 bytes) bits 7C0 cmos data (128 bytes) bits 7C0 cmos data (256 bytes) cmos address port 70h wo bit 7654321bit 0 bit name nmid cmos address reset00000000 cmos data port 71h rw bit 7654321bit 0 bit name cmos data reset00000000 cmos data port 72h, port 73h, port 74h, and port 75h rw bit 7654321bit 0 bit name cmos data reset00000000
registers 7-15 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7.3 function 0 registers (pci-isa bridge) 7.3.1 function 0 pci configuration space header the vendor id is a read-only register containing the value 1106h. the device id is a read-only register containing the value 0586h. bits 15C4 reserved (always reads 0) bit 3 special cycle enable (normally rw see note) 1 = enabled (default) 0=disabled bit 2 bus master (always reads 0) 1 = enabled (default) 0=disabled bit 1 memory space (normally ro, reads 1 see note) 1 = enabled (default) 0=disabled bit 0 i/o space (normally ro, reads 1 see note) 1 = enabled (default) 0=disabled note: if the test bit at offset 46h, bit 4 is set, access to the bits indicated above is reversed: bit 3 above becomes read only (reading back 1) and bits 0 C 1 above become read/write (with a default of 1). vendor id function 0 offset 01hC00h ro bit 1514131211109 8 7654321bit 0 vendor id reset0001000100000110 device id function 0 offset 03hC02h ro bit 1514131211109 8 7654321bit 0 device id reset0000010110000110 command function 0 offset 05hC04h rw bit 1514131211109 8 7654321bit 0 reserved sce bm ms ios reset0000000000001111
7-16 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 15 detected parity error (write 1 to clear) bit 14 signalled system error (always reads 0) bit 13 signalled master abort (always reads 0) bit 12 received target abort (always reads 0 - write 1 to clear) bit 11 signalled target abort (always reads 0) bit 10 C 9 devsel# timing (fixed at 01 = medium) bit 8 data parity detected (always reads 0) bit 7 fast back-to-back (always reads 0) bits 6C0 reserved (always reads 0) the revision id is a read-only register containing the revision number. the program interface is a read-only register containing the value 00h. the sub class code is a read-only register containing the value 01h. status function 0 offset 07hC06h rwc bit 1514131211109 8 7654321bit 0 dpe sse sma rta sta devsel# dpd fbtb reserved reset0000001000000000 revision id function 0 offset 08h ro bit 7654321bit 0 bit name revision number resetnnnnnnnn program interface function 0 offset 09h ro bit 7654321bit 0 bit name 00h reset00000000 sub class code function 0 offset 0ah ro bit 7654321bit 0 bit name 01h reset00000001
registers 7-17 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the class code is a read-only register containing the value 06h. the header type is a read-only register containing the value 80h. bist is a read-only register containing the value 00h. 7.3.2 isa bus control bit 7 isa command delay 1 = extra delay 0 = normal delay (default) bit 6 extended isa bus ready 1 = enable 0 = disable (default) bit 5 isa slave wait states 1 = 5 wait states 0 = 4 wait states (default) class code function 0 offset 0bh ro bit 7654321bit 0 bit name 06h reset00000110 header type function 0 offset 0eh ro bit 7654321bit 0 bit name 80h reset10000000 bist function 0 offset 0fh ro bit 7654321bit 0 bit name 00h reset00000000 isa bus control function 0 offset 40h rw bit 7654321bit 0 bit name cd br sws iows iort eale rws romw reset00000000
7-18 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 4 chipset i/o wait states 1 = 4 wait states 0 = 2 wait states (default) bit 3 i/o recovery time 1 = enable 0 = disable (default) bit 2 extend ale 1 = enable 0 = disable (default) bit 1 rom wait states 1 = 0 wait states 0 = 1 wait state (default) bit 0 rom write 1 = enable 0 = disable (default) bits 7C6 reserved (always reads 0) bit 5 port 92 fast reset 1 = enable 0 = disable (default) bit 4 reserved (always reads 0) bit 3 double dma clock 1 = enable (dma clock = isa clock) 0= disable (dma clock = ?) (default) bits 2C0 reserved (always reads 0) bit 7 latch io16# 1=disable 0 = enable (recommended) (default) bits 6C4 reserved (always reads 0) sa test mode function 0 offset 41h rw bit 7654321bit 0 bit name reserved p92fr reserved ddmac reserved reset00000000 isa clock control function 0 offset 42h rw bit 7654321bit 0 bit name lio16 reserved icse isacs reset00000000
registers 7-19 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 3 isa bus clock select enable 1 = isa clock selected per bits 2 C 0 0 = isa clock = pclk/4 (default) bits 2C0 isa bus clock select (when bit 3 = 1) 000 = pclk/3 (default) 001 = pclk/2 010 = pclk/4 011 = pclk/6 100 = pclk/5 101 = pclk/10 110 = pclk/12 111 = osc/2 note: to switch the isa clock, take the following steps: 1. clear bit 3 of this register. 2. change the value of bits 2C0 to reflect the desired clock. 3. set bit 3. setting the following bits enables the indicated address range to be included in the romcs# decode: bit 7 fffe0000hCfffe ffffh 1 = enable 0 = disable (default) bit 6 fff80000hCfffdffffh 1 = enable 0 = disable (default) bit 5 000e8000hC000e ffffh 1 = enable 0 = disable (default) bit 4 000e0000hC000e7fffh 1 = enable 0 = disable (default) bit 3 000d8000hC000dffffh 1 = enable 0 = disable (default) rom decode control function 0 offset 43h rw bit 7654321bit 0 bit name rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 reset00000000
7-20 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 2 000d0000hC000d7fffh 1 = enable 0 = disable (default) bit 1 000c8000hC000cffffh 1 = enable 0 = disable (default) bit 0 000c0000hC000c7fffh 1 = enable 0 = disable (default) bits 7C4 reserved (always reads 0) bit 3 mouse lock enable 1 = enable 0 = disable (default) bits 2C0 reserved setting the following bits enables dma type f timing on the indicated dma channels. bit 7 isa master/dma to pci line buffer 1 = enable 0 = disable (default) bit 6 dma type f timing on channel 7 1 = enable 0 = disable (default) bit 5 dma type f timing on channel 6 1 = enable 0 = disable (default) bit 4 dma type f timing on channel 5 1 = enable 0 = disable (default) keyboard controller control function 0 offset 44h rw bit 7654321bit 0 bit name reserved mle reserved reset00000000 type f dma control function 0 offset 45h rw bit 7654321bit 0 bit name lb ch7 ch6 ch5 ch3 ch2 ch1 ch0 reset00000000
registers 7-21 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 3 dma type f timing on channel 3 1 = enable 0 = disable (default) bit 2 dma type f timing on channel 2 1 = enable 0 = disable (default) bit 1 dma type f timing on channel 1 1 = enable 0 = disable (default) bit 0 dma type f timing on channel 0 1 = enable 0 = disable (default) bits 7C5 reserved (always reads 0) bit 4 configure command register offset 05hC04h access (test only) 1= test mode: command register bits 0C1 are rw, bit 3 is ro 0 = normal mode: command register bits 0C1 are ro, bit 3 is rw bits 3C2 reserved (always reads 0) bit 1 pci burst read interruptability 1 = disallow pci burst read interrupting 0 = allow burst reads to be interrupted (default) bit 0 post memory write enable 1 = enable 0 = disable (default) bit 7 cpu reset source 1 = use init as cpu reset 0 = use cpurst (default) bit 6 pci delaytransaction enable 1 = enable 0 = disable (default) miscellaneous control 1 function 0 offset 46h rw bit 7654321bit 0 bit name reserved cc04 reserved bri pmwe reset00000 00 miscellaneous control 2 function 0 offset 47h rw bit 7654321bit 0 bit name rs dte pe icsre reserved wdte rdte pcirst reset00000000
7-22 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 5 eisa 4d0/4d1 port enablerw 1= enable (ports 4d0hC4d1h per eisa specification) 0 = disable (ignore ports 4d0C4d1h) (default) bit 4 interrupt controller shadow register enable 1 = enable 0 = disable (default) bit 3 reserved (always reads 0) bit 2 write delay transaction time-out timer enable 1 = enable 0 = disable (default) bit 1 read delay transaction time-out timer enable 1 = enable 0 = disable (default) bit 0 software pci reset setting this bit causes a pci reset by asserting the pcirst pin. bits 7C4 reserved (always reads 0) bit 3 extra rtc port 74/75 enable 1=disable 0 = enable (default) bit 2 integrated usb controller disable 1=disable 0 = enable (default) bit 1 integrated ide controller disable 1=disable 0 = enable (default) bit 0 512k pci memory decode 1= use the contents of bits 15C12 of offset 4eh plus 512 kbytes as the top of pci memory (default) 0 = use the contents of bits 15C12 of offset 4eh as the top of pci memory miscellaneous control 3 function 0 offset 48h rw bit 7654321bit 0 bit name reserved ex74/75 iusbcd iidecd pcimd reset00000001
registers 7-23 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 7 wait for pgnt before grant to isa master/dma 1 = enable (must be set) 0 = disable (default) bit 6 bus select for i/o devices below 100h 1 = access ports 00h C ffh via xd bus 0 = access ports 00h C ffh via sd bus bits 5C4 reserved (always reads 0) bits 3C2 ide second channel irq routing 00 = irq14 01 = irq15 (default) 10 = irq10 11 = irq11 bits 1C0 ide primary channel irq routing 00 = irq14 (default) 01 = irq15 10 = irq10 11 = irq11 the bits in this register correspond to ha23Cha16. bits 7C0 pci memory hole bottom address the bits in this register correspond to ha23Cha16. bits 7C0 pci memory hole top address note: access to the memory defined in the pci memory hole will not be forwarded to pci. this function is disabled if the top address is less than or equal to the bottom address. ide interrupt routing function 0 offset 4ah rw bit 7654321bit 0 bit name wpgnt bsio reserved idesch idepch reset00000100 isa dma/master memory access control 1 function 0 offset 4ch rw bit 7654321bit 0 bit name bit values correspond to ha23Cha16 (default = 00h) reset00000000 isa dma/master memory access control 2 function 0 offset 4dh rw bit 7654321bit 0 bit name bit values correspond to ha23Cha16 (default = 00h) reset00000000
7-24 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information isa dma/master memory access control 3 is a rw register. bits 15C12 top of pci memory for isa dma/master accesses 0000 = 1 mbyte (default) 0001 = 2 mbytes ... 1111 = 16 mbytes note: isa dma/masters that access addresses higher than the top of pci will not be directed to the pci bus. bit 11 forward e0000hCe ffffh accesses to pci (default = 0) bit 10 forward a0000hCb ffffh accesses to pci (default = 0) bit 9 forward 80000hC9 ffffh accesses to pci (default = 1) bit 8 forward 00000hC7 ffffh accesses to pci (default = 1) bit 7 forward dc000hCdffffh accesses to pci (default = 0) bit 6 forward d8000hCdbfffh accesses to pci (default = 0) bit 5 forward d4000hCd7fffh accesses to pci (default = 0) bit 4 forward d0000hCd3fffh accesses to pci (default = 0) bit 3 forward cc000hCcffffh accesses to pci (default = 0) bit 2 forward c8000hCcbfffh accesses to pci (default = 0) bit 1 forward c4000hCc7fffh accesses to pci (default = 0) bit 0 forward c0000hCc3fffh accesses to pci (default = 0) 7.3.3 plug-n-play control registers bits 7C0 reserved (always reads 04h) isa dma/master memory access control 3 function 0 offset 4fhC4eh bit 1514131211109 8 7654321bit 0 reset0000001100000000 pnp drq routing function 0 offset 50h rw bit 7654321bit 0 bit name reserved (default = 04h) reset00000100
registers 7-25 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bits 7C4 reserved (always reads 0) bit 3 pirqa# invert (edge)/non-invert (level) 1=edge 0 = level (default) bit 2 pirqb# invert (edge)/non-invert (level) 1=edge 0 = level (default) bit 1 pirqc# invert (edge)/non-invert (level) 1=edge 0 = level (default) bit 0 pirqd# invert (edge)/non-invert (level) 1=edge 0 = level (default) bits 7C4 mirq1 routing 0000 = disabled (default) 0001 = irq1 0010 = reserved 0011 = irq3 0100 = irq4 0101 = irq5 0110 = irq6 0111 = irq7 1000 = reserved 1001 = irq9 1010 = irq10 1011 = irq11 1100 = irq12 1101 = reserved 1110 = irq14 1111 = irq15 bits 3C0 mirq0 routing (same as mirq1 routing) pci irq edge/level select function 0 offset 54h rw bit 7654321bit 0 bit name reserved pirqa pirqb pirqc pirqd reset00000000 pnp irq routing 1 function 0 offset 55h rw bit 7654321bit 0 bit name mirqd routing mirq0 routing reset00000000
7-26 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bits 7C4 pirq# routing (same as mirq1 routing) bits 3C0 pirqa# routing (same as mirq1 routing) bits 7C4 pirqd# routing (same as mirq1 routing) bits 3C0 pirqc# routing (same as mirq1 routing) bits 7C4 reserved (always reads 0) bits 3C0 mirq2 routing (same as mirq1 routing) bits 7C3 reserved (always reads 0) bits 2 mirq2/master# selection 0 = mirq2 (default) 1=master# bits 1 mirq1/keylock selection 0 = mirq1 (default) 1 = keylock bits 0 mirq0/apiccs# selection 0 = mirq0 (default) 1 = apiccs# pnp irq routing 2 function 0 offset 56h rw bit 7654321bit 0 bit name pirqb routing pirqa routing reset00000000 pnp irq routing 3 function 0 offset 57h rw bit 7654321bit 0 bit name pirqd routing pirqc routing reset00000000 pnp irq routing 4 function 0 offset 58h rw bit 7654321bit 0 bit name reserved mirq2 routing reset00000000 mirq pin configuration function 0 offset 59h rw bit 7654321bit 0 bit name reserved mirq/alternate function reset00000000
registers 7-27 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the values in the bits of this register are latched from pins xd7Cxd0 at power-up, but can be accessed after power-up to change the strapped settings. bit 7 keyboard rp16 (latched from xd7) bit 6 keyboard rp15 (latched from xd6) bit 5 keyboard rp14 (latched from xd5) bit 4 keyboard rp13 (latched from xd4) bit 3 reserved (always reads 0) bit 2 internal rtc enable (latched from xd2) 1 = enable 0=disable bit 1 internal ps2 mouse enable (latched from xd1) 1 = enable 0=disable bit 0 internal kbc enable ( latched from xd0) 1 = enable 0=disable note: external strap option values can be set by connecting the indicated external pin to ground or through a 4.7-kohm pullup to v cc (for 1) or driving it low with a 7407 ttl open-collector buffer (for 0) as shown in figure 7-1. figure 7-1. strap option circuit xd power-up strap options function 0 offset 5ah rw bit 7654321bit 0 bit name krp16 krp15 krp14 krp13 reserved irtce ips2me ikbce reset xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 4.7k v cc v cc reset# 7407
7-28 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bits 7C2 reserved (always reads 0) bit 1 rtc sram access enable this bit is set to access the internal rtc sram via ports 74h/75h while the internal rtc is disabled. if the internal rtc is enabled, setting this bit has no effect, and the internal rtc sram should be accessed at either ports 70h/71h or ports 72h/73h. 1 = enable 0 = disable (default) bit 0 reserved (always reads 0) 7.3.4 distributed dma control distributed dma ch 0 base/enable function 0 offset 61hC60h rw distributed dma ch 1 base/enable function 0 offset 63hC62h rw distributed dma ch 2 base/enable function 0 offset 65hC64h rw distributed dma ch 3 base/enable function 0 offset 67hC66h rw distributed dma ch 5 base/enable function 0 offset 6bhC6ah rw distributed dma ch 6 base/enable function 0 offset 6dhC6ch rw distributed dma ch 7 base/enable function 0 offset 6fhC6eh rw bits 15C4 channel n base address bits 15C4 0000 = default bit 3 channel n enable 1 = enable 0 = disable (default) bits 2C0 reserved (always reads 0) internal rtc test mode function 0 offset 5bh rw bit 7654321bit 0 bit name reserved rtcsae reserved reset00000000 bit 1514131211109 8 7654321bit 0 channel n base address bits 15C4 ce reserved reset0000000000000000
registers 7-29 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7.4 function 1 registers (enhanced ide controller) all eide controller registers are located in function 1 of the AMD-645 peripheral bus controller pci configuration space and are accessed through pci configuration mechanism #1 via address 0cf8h/0cfch. the AMD-645 peripheral bus controller enhanced ide controller interface is fully compatible with the sff 8038i v.1.0 specification. there are two sets of software-accessible registers, the pci configuration registers and the bus master ide i/o registers. 7.4.1 function 1 pci configuration space header the vendor id is a read-only register containing the value 1106h. the device id is a read-only register containing the value 0571h. bits 15C10 reserved (always reads zero) bit 9 fast back-to-back cycles (fixed at 0) 1 = enabled 0 = disabled (default) bit 8 serr# enable (fixed at 0) 1 = enabled 0 = disabled (default) vendor id function 1 offset 01hC00h ro bit 1514131211109 8 7654321bit 0 vendor id reset0001000100000110 device id function 1 offset 03hC02h ro bit 1514131211109 8 7654321bit 0 value 0571h reset0000010101110001 command function 1 offset 05hC04 rwh bit 1514131211109 8 7654321bit 0 reserved fbbc se as per ps mwi sce bm ms ios reset0000000010000000
7-30 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 7 address stepping (fixed at 1) 1 = enabled (default) 0=disabled bit 6 parity error response (fixed at 0) 1 = enabled 0 = disabled (default) bit 5 vga pallette snoop (fixed at 0) 1 = enabled 0 = disabled (default) bit 4 memory write & invalidate (fixed at 0) 1 = enabled 0 = disabled (default) bit 3 special cycles (fixed at 0) 1 = enabled 0 = disabled (default) bit 2 bus master (sg operation can be issued only when this bit is enabled.) 1 = enabled 0 = disabled (default) bit 1 memory space (fixed at 0) 1 = enabled 0 = disabled (default) bit 0 i/o space (default = 0 = disabled) when this bit is disabled, the device does not respond to any i/o addresses for either compatible or native mode. bit 15 detected parity error (default = 0) bit 14 signalled system error (default = 0) bit 13 signalled master abort (default = 0) bit 12 received target abort (default = 0) bit 11 signalled target abort (roalways reads 0) bits 10C9 devsel# timing 00 = fast 01 = medium (default) 10 = slow 11 = reserved bit 8 data parity detected (default = 0) bit 7 fast back-to-back (roalways reads 1) status function 1 offset 07hC06h rwc bit 1514131211109 8 7654321bit 0 dpe sse rma rta sta dt dpd fbtb reserved reset0000001000000000
registers 7-31 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bits 6C0 reserved (always reads 0) the revision id is a read-only register containing the revision code for the ide controller logic block. bit 7 master ide capability (fixed at 1 - supported) bits 6C4 reserved (always reads 0) bit 3 secondary programmable indicator (fixed at 1) 1 = supports both modes (mode is selected by writing bit 2) 0 = fixed (compatibility or native pci mode is determined by bit 2) bit 2 secondary channel operating mode 1 = native pci mode (default when spkr=1) 0 = compatibility mode (default when spkr=0) the default value for this bit is determined at power-up by the strapping at the spkr pin, pin 134. the strapping determines whether ide addressing is fixed (1) or flexible (0). (see figure 7-1 on page 7-27 for a drawing of a strap circuit). after reset, bit 2 can be written to determine the channel operating mode. table 7-10 summarizes the differences between native pci and compatibility modes. revision id function 1 offset 08 roh bit 7654321bit 0 bit name revision code for ide controller logic block resetnnnnnnnn programming interface function 1 offset 09h rw bit 7654321bit 0 bit name midec reserved spi scom ppi pcom reset10001x1x table 7-10. compatibility mode vs. native pci mode mode command block registers control block registers irq compatibility mode primary fixed at i/o offset 1f7hC1f0h fixed at i/o offset 3f6h 14 secondary fixed at i/o offset 177hC170h fixed at i/o offset 376h 15 native pci mode primary determined by offset 10h determined by offset 14h secondary determined by offset 18h determined by offset 1ch notes: command register blocks are 8 bytes of i/o space, while control registers are 4 bytes of i/o space (only byte 2 is used).
7-32 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 1 primary programmable indicator (fixed at 1) 1 = supports both modes (mode is selected by writing bit 0) 0 = fixed (compatibility or native pci mode is determined by bit 2) 1 = native pci mode (default when spkr=1) 0 = compatibility mode (default when spkr=0) bit 0 primary channel operating mode 1 = native pci mode (default when spkr=1) 0 = compatibility mode (default when spkr=0) the sub class code is a read-only register containing the value 01h. the base class code is a read-only register containing the value 01h. the latency timer is a read-write register that defaults to 0. the header type is a read-only register containing the value 00h. sub class code function 1 offset 0ah ro bit 7654321bit 0 bit name 01h reset00000001 base class code function 1 offset 0bh ro bit 7654321bit 0 bit name 01h reset00000001 latency timer function 1 offset 0dh rw bit 7654321bit 0 bit name 00h reset00000000 header type function 1 offset 0eh ro bit 7654321bit 0 bit name 00h reset10000000
registers 7-33 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the bist is a read-only register containing the value 00h. the primary data/command base address is a read-write register that specifies an 8-byte i/o address space. bits 31C16 reserved (always reads 0) bits 15C3 port address (default = 01f0h) bits 2C0 value fixed at 001binary the primary control/status base address is a read-write register that specifies a 4-byte i/o address space, of which only the third byte is active. for example, 3f6h is the active byte for the default base address of 3f4h. bits 31C16 reserved (always reads 0) bits 15C2 port address (default = 03f4h) bits 1C0 value fixed at 01binary bist function 1 offset 0fh ro bit 7654321bit 0 bit name 00h reset00000000 primary data/command base address function 1 offset 13hC10h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 port address fixed reset0000000111110001 primary control/status base address function 1 offset 17hC14h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 port address fixed reset0000001111110101
7-34 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information the secondary data/command base address is a read-write register that specifies an 8-byte i/o address space. bits 31C16 reserved (always reads 0) bits 15C3 port address (default = 0170h) bits 2C0 value fixed at 001binary the secondary control/status base address is a read-write register that specifies a 4-byte i/o address space, of which only the third byte is active. for example, 376h is the active byte for the default base address of 374h. bits 31C16 reserved (always reads 0) bits 15C2 port address (default = 374h) bits 1C0 value fixed at 01 binary the bus master control registers base address is a read-write register that specifies a 16-byte i/o address space which is compliant with the sff 8038i rev. 1.0 specification. secondary data/command base address function 1 offset 1bhC18h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 port address fixed reset0000000101110001 secondary control/status base address function 1 offset 1fhC1ch rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 port address fixed reset0000001101110101 bus master control registers base address rw function 1 offset 23hC20h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 port address fixed reset1100110000000001
registers 7-35 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bits 31C16 reserved (always reads 0) bits 15C4 port address ( default = cc0h) bits 3C0 value fixed at 0001 binary the interrupt line is a read-write register containing the default value 0eh. the interrupt pin is a read-only register that defines the interrupt routing mode. bits 7C0 interrupt routing mode 00h =legacy mode interrupt routing (default) 01h =native mode interrupt routing min gnt is a read-only register containing the value 00h. max latency is a read-only register containing the value 00h. interrupt line function 1offset 3ch rw bit 7654321bit 0 bit name 0eh reset00001110 interrupt pin function 1 offset 3dh ro bit 7654321bit 0 bit name irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 reset00000000 min gnt function 1 offset 3eh ro bit 7654321bit 0 bit name 00h reset00000000 max latency function 1 offset 3fh ro bit 7654321bit 0 bit name 00h reset00000000
7-36 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 7.4.2 ide controller-specific configuration registers chip enable is a read-write control register used to enable the primary or secondary channel. bits 7C2 reserved (always reads 000001 binary) bit 1 primary channel enable 1 = enabled 0 = disabled (default) bit 0 secondary channel enable 1 = enabled 0 = disabled (default) ide configuration is a read-write control register that defaults to 06h. bit 7 primary ide read prefetch buffer 1 = enabled 0 = disabled (default) bit 6 primary ide post write buffer 1 = enabled 0 = disabled (default) bit 5 secondary ide read prefetch buffer 1 = enabled 0= disabled (default) bit 4 secondary ide post write buffer 1 = enabled 0 = disabled (default) bits 3C0 reserved (always reads 0110 binary). although they are read-write, the value of these bits should never be changed.) reserved (do not program) function 1 offset 42h rw the reserved register at function 1, offset 42h is a read-write register that should not be programmed. chip enable function 1 offset 40h rw bit 7654321bit 0 bit name reserved pce sce reset00000100 ide configuration function 1 offset 41h rw bit 7654321bit 0 bit name prpb ppwb srpb spwb reserved reset00000110
registers 7-37 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information first-in-first-out (fif0) configuration is a read-write control register. bit 7 reserved (always reads 0) bits 6C5 fifo configuration these bits determine fifo distribution as shown in table 7-11. bit 4 reserved (always reads 1) bits 3C2 threshhold for primary channel 00 = 1 01 = 3/4 10 = 1/2 (default) 11 = 1/4 bits 1C0 threshhold for secondary channel 00 = 1 01 = 3/4 10 = 1/2 (default) 11 = 1/4 bit 7 reserved (always reads 0) bit 6 master read cycle irdy# wait states 1 = 1 wait state (default) 0 = 0 wait states fifo configuration function 1 offset 43h rw bit 7654321bit 0 bit name reserved. fifo configuration reserved tpc tsc reset00111010 table 7-11. fifo distribution bits 6, 5 primary channel secondary channel 00 16 0 01(default) 8 8 10 8 8 11 0 16 miscellaneous control 1 function 1 offset 44h rw bit 7654321bit 0 bit name rsvd. mrcws mwcws ca srrr reserved reset01101000
7-38 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 5 master write cycle irdy# wait states 1 = 1 wait state (default) 0 = 0 wait states bit 4 fifo output data 1/2 clock advance 1 = enabled 0 = disabled (default) bit 3 bus master ide status register read retry 1 = enabled (default) 0=disabled bits 2C0 reserved (always reads 0) bit 7 reserved (always reads 0) bit 6 interrupt steering swap 1 = swap interrupts between the two channels (default) 0 = do not swap channel interrupts bits 5C0 reserved (always reads 0) bit 7 primary channel read dma fifo flush 1 = enable fifo flush for read dma when interrupt asserts primary channel (default) 0=disable bit 6 secondary channel read dma fifo flush 1 = enable fifo flush for read dma when interrupt asserts secondary channel (default) 0=disable bit 5 primary channel end-of-sector fifo flush 1 = enable fifo flush at the end of each sector for the primary channel 0 = disable (default) bit 4 secondary channel end-of-sector fifo flush 1 = enable fifo flush at the end of each sector for the secondary channel 0 = disable (default) miscellaneous control 2 function 1 offset 45h rw bit 7654321bit 0 bit name rsvd. iss reserved reset00000000 miscellaneous control 3 function 1 offset 46h rw bit 7654321bit 0 bit name pcr scr pce sce reserved mpw reset11000000
registers 7-39 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bits 3C2 reserved (always reads 0) bits 1C0 max drdy# pulse width maximum drdy# pulse width after the cycle count. command will deassert in spite of drdy# status to avoid hanging the system. 00 = no limitation (default) 01 = 64 pci clocks 10 = 128 pci clocks 11 = 192 pci clocks each field of this register defines the active pulse width and recovery time for a particular ide dior# or diow# signal. the actual value for each field is the encoded value plus one, and indicates the number of pci clocks. bits 31C28 primary drive 0 active pulse width (default = 1010 binary) bits 27C24 primary drive 0 recovery time (default = 1000 binary) bits 23C20 primary drive 1 active pulse width (default = 1010 binary) bits 19C16 primary drive 1 recovery time (default = 1000 binary) bits 15C12 secondary drive 0 active pulse width (default = 1010 binary) bits 11C8 secondary drive 0 recovery time (default = 1000 binary) bits 7C4 secondary drive 1 active pulse width (default = 1010 binary) bits 3C0 secondary drive 1 recovery time (default = 1000 binary) drive timing control function 1 offset 4bhC48 rwh bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 pd0apw pd0rt pd1apw pd1rt reset1010100010101000 bit 1514131211109 8 7654321bit 0 sd0apw sd0rt sd1apw sd1rt reset1010100010101000
7-40 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bits 7C6 primary drive 0 address setup time bits 5C4 primary drive 1 address setup time bits 3C2 secondary drive 0 address setup time bits 1C0 secondary drive 1 address setup time each of these bit pairs defines the corresponding address setup time as follows: 00 = 1t 01 = 2t 10 = 3t 11 = 4t (default) the actual value in the field is the encoded value in the field plus one. this value indicates the number of pci clocks. bits 7C4 dior#/diow# active pulse width (default = 1111 binary) bits 4C0 dior#/diow# recovery time (default = 1111 binary) the actual value is the encoded value in the field plus one. this value indicates the number of pci clocks. bits 7C4 dior#/diow# active pulse width (default = 1111 binary) bits 4C0 dior#/diow# recovery time (default = 1111 binary) address setup time function 1 offset 4ch rw bit 7654321bit 0 bit name pd0ast pd1ast sd0ast sd1ast reset01101000 secondary non-1f0 port access timing function 1 offset 4eh rw bit 7654321bit 0 bit name active pulse width recovery time reset11111111 primary non-1f0 port access timing function 1 offset 4fh rw bit 7654321bit 0 bit name active pulse width recovery time reset11111111
registers 7-41 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information each byte of these registers defines ultra dma-33 operation for the indicated drive. the bit definitions are consistent within each byte. bit 31 primary drive 0 ultra dma-33 mode enable method 1 = enable by setting bit 6 of this register 0 = enable by using the set feature command (default) bit 30 primary drive 0 ultra dma-33 mode enable 1 = enable ultra dma-33 mode operation 0 = disable (default) bit 29 primary drive 0 ultra dma-33 transfer mode 1 = transfer based on ultra dma-33 pio mode 0 = based on ultra dma-33 dma mode (default) bits 28C26 reserved (always reads 0) bits 25C24 primary drive 0 cycle time 00 = 2t 01 = 3t 10 = 4t 11 = 5t (default) bit 23 primary drive 1 ultra dma-33 mode enable method 1 = enable by setting bit 6 of this register 0 = enable by using the set feature command (default) bit 22 primary drive 1ultra dma-33 mode enable 1 = enable ultra dma-33 mode operation 0 = disable (default) bit 21 primary drive 1 ultra dma-33 transfer mode 1 = transfer based on ultra dma-33 pio mode 0 = based on ultra dma-33 dma mode (default) bits 20C18 reserved (always reads 0) bits 17C16 primary drive 1 cycle time 00 = 2t 01 = 3t 10 = 4t 11 = 5t (default) ultra dma-33 extended timing control function 1 offset 53hC50h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 primary drive 0 primary drive 1 reset0000001100000011 bit 1514131211109 8 7654321bit 0 secondary drive 0 secondary drive 1 reset1100001100000011
7-42 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 15 secondary drive 0 ultra dma-33 mode enable method 1 = enable by setting bit 6 of this register 0 = enable by using the set feature command (default) bit 14 secondary drive 0 ultra dma-33 mode enable 1 = enable ultra dma-33 mode operation 0 = disable (default) bit 13 secondary drive 0 ultra dma-33 transfer mode 1 = transfer based on ultra dma-33 pio mode 0 = based on ultra dma-33 dma mode (default) bits 12C10 reserved (always reads 0) bits 9C8 secondary drive 0 cycle time 00 = 2t 01 = 3t 10 = 4t 11 = 5t (default) bit 7 secondary drive 1 ultra dma-33 mode enable method 1 = enable by setting bit 6 of this register 0 = enable by using the set feature command (default) bit 6 secondary drive 1ultra dma-33 mode enable 1 = enable ultra dma-33 mode operation 0 = disable (default) bit 5 secondary drive 1 ultra dma-33 transfer mode 1 = transfer based on ultra dma-33 pio mode 0 = based on ultra dma-33 dma mode (default) bits 4C2 reserved (always reads 0) bits 1C0 secondary drive 1 cycle time 00 = 2t 01 = 3t 10 = 4t 11 = 5t (default) the primary sector size is a read-write control register whose bits 11 C 0 determine the size of each primary sector. the value of these bits defaults to 200h. primary sector size function 1 offset 61hC60h rw bit 1514131211109 8 7654321bit 0 reserved number of bytes per sector reset0000001000000000
registers 7-43 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information the secondary sector size is a read-write control register whose bits 11 C 0 determine the size of each secondary sector. the value of these bits defaults to 200h. 7.4.3 ide i/o registers the ide i/o registers comply with the sff 8038i v. 1.0 standard. the base address of these registers is determined by configuration register function 1, offset 09h (see page 7-31). the command block primary channel is 1f0hC1f7h, while the secondary channel is 170hC177h. refer to the specification for further details. primary channel command is an i/o register. primary channel status is an i/o register. the primary channel prd table address is an i/o register. secondary sector size function 1 offset 69hC68h rw bit 1514131211109 8 7654321bit 0 reserved number of bytes per sector reset0000001000000000 primary channel command function 1 offset 00h bit 7654321bit 0 bit name primary channel command reset primary channel status function 1 offset 02h bit 7654321bit 0 bit name primary channel status reset00000000 primary channel prd table address function 1 offset 07hC04h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 primary channel prd table address reset0000000000000000 bit 1514131211109 8 7654321bit 0 primary channel prd table address reset0000000000000000
7-44 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information secondary channel command is an i/o register. secondary channel status is an i/o register. the secondary channel prd table address is an i/o register. 7.5 function 2 registers (usb controller) all universal serial bus (usb) controller registers are located in function 2 of the AMD-645 peripheral bus controller pci configuration space and are accessed through pci configuration mechanism #1 via address 0cf8h/0cfch. this usb host controller interface is fully compatible with uhci specification v. 1.1 . there are two sets of software accessible-registers, pci configuration registers and usb i/o registers. secondary channel command function 1 offset 08h bit 7654321bit 0 bit name secondary channel command reset secondary channel status function 1 offset 0ah bit 7654321bit 0 bit name secondary channel status reset00000000 secondary channel prd table address function 1 offset 0fhC0ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 secondary channel prd table address reset0000000000000000 bit 1514131211109 8 7654321bit 0 secondary channel prd table address reset0000000000000000
registers 7-45 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 7.5.1 function 2 pci configuration space header the vendor id is a read-only register containing the value 1106h. the device id is a read-only register containing the value 3038h. bits 15C8 reserved ( always reads zero) bit 7 address stepping 1 = enabled 0 = disabled (default) bit 6 reserved (parity error response - fixed at 0) bit 5 reserved (vga pallette snoop - fixed at 0) bit 4 memory write & invalidate 1 = enabled 0 = disabled (default) bit 3 reserved (special cycle monitoring - fixed at 0) bit 2 bus master 1 = enabled 0 = disabled (default) bit 1 memory space 1 = enabled 0 = disabled (default) bit 0 i/o space 1 = enabled 0 = disabled (default) vendor id function 2 offset 01hC00h ro bit 1514131211109 8 7654321bit 0 vendor id reset0001000100000110 device id function 2 offset 03hC02h ro bit 1514131211109 8 7654321bit 0 value 3038h reset0011000000111000 command function 2 offset 05hC04h rw bit 1514131211109 8 7654321bit 0 reserved as reserved mwi rsvd. bm ms ios reset0000000000000000
7-46 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 15 reserved (detected parity error - always reads 0) bit 14 signalled system error (default = 0) bit 13 received master abort (default = 0) bit 12 received target abort (default = 0) bit 11 signalled target abort (default = 0) bit 10C9 devsel# timing 00 = fast 01 = medium (default) 10 = slow 11 = reserved bits 8C0 reserved (always reads 0) revision id is a read-only register containing the silicon revision code, where the value 00h indicates first silicon. programming interface is a read-only register containing the value 00h. sub class code is a read-only register containing the value 03h. status function 2 offset 07hC06h rwc bit 1514131211109 8 7654321bit 0 rsvd. sse rma rta sta devsel# reserved reset0000001000000000 revision id function 2 offset 08h ro bit 7654321bit 0 bit name silicon revision code reset programming interface function 2 offset 09h ro bit 7654321bit 0 bit name 00h reset00000000 sub class code function 2 offset 0ah ro bit 7654321bit 0 bit name 03h reset00000011
registers 7-47 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information class code is a read-only register containing the value 0ch. latency timer is a read-write register containing the default 16h. header type is a read-only register containing the value 00h. bits 15C5 of this register are used to set the port address for the base of the usb i/o register block, corresponding to ad15Cad5. bits 31C16 reserved (always reads 0) bits 15C5 usb i/o register base address bits 4C0 fixed (value of these bits is set at 00001 binary) base class code function 2 offset 0bh ro bit 7654321bit 0 bit name 0ch reset00001100 latency timer function 2 offset 0dh rw bit 7654321bit 0 bit name 16h reset00010110 header type function 2 offset 0eh ro bit 7654321bit 0 bit name 00h reset00000000 usb i/o register base address function 2 offset 23hC20h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 usb i/o register base address fixed reset1100110000000001
7-48 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information interrupt line is a read-write register containing the default 00h. interrupt pin is a read-only register containing the value 04h. 7.5.2 usb-specific configuration registers bit 7 pci memory command option 1 = support memory read and memory write commands only 0 = support memory-read-line, memory-read-multiple, and memory-write-and-invalidate commands (default) bit 6 babble option 1 = do not disable babbled port 0 = disable babbled port when eof babble occurs (default) bit 5 pci parity check option 1 = enable parity check and perr# generation 0 = disable parity check and perr# generation (default) bit 4 reserved (always reads 0) bit 3 usb data length option 1 = support td length up to 1023 0 = support td length up to 1280 (default) bit 2 usb power management 1 = enable usb power management 0 = disable usb power management (default) interrupt line function 2 offset 3ch rw bit 7654321bit 0 bit name 00h reset00010110 interrupt pin function 2 offset 3dh ro bit 7654321bit 0 bit name 04h reset00000100 miscellaneous control 1 function 2 offset 40h rw bit 7654321bit 0 bit name mco bo pco rsvd. dlo pm dmao ws reset00000000
registers 7-49 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 1 dma option 1 = 8-dw burst access 0 = 16-dw burst access (default) bit 0 pci wait states 1=1 wait state 0 = 0 wait states (default) bits 7C3 reserved (always reads 0) bit 2 trap option 1 = set trap 60/64 bits only when trap 60/64 enable bits are set 0 = set trap 60/64 status bits without checking the enable bits (default) bit 1 a20gate pass through option 1 = do not pass through i/o port 64h 0 = pass through the a20gate command sequence defined in uhci (default) bit 0 reserved (always reads 0) serial bus release number is a read-only register that defaults to a value of 10h. legacy support is a read-only register. to achieve uhci v. 1.1 compliance, the value of this register is fixed at 2000h. miscellaneous control 2 function 2 offset 41h rw bit 7654321bit 0 bit name reserved to a20pto reserved reset00000000 serial bus release number function 2 offset 60h ro bit 7654321bit 0 bit name release number reset00010000 legacy support function 2 offset c1hCc0h ro bit 1514131211109 8 7654321bit 0 fixed reset0010000000000000
7-50 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 7.5.3 usb i/o registers these registers are compliant with the uhci v. 1.1 standard. the usb i/o register base address register at function 0, offset 23hC20h is used to program the base address to which each of the usb i/o registers is offset. refer to the specification for further details. usb command is an i/o register. usb status is an i/o register. usb interrupt enable is an i/o register. frame number is an i/o register. frame list base address is an i/o register. usb command function 2 offset 01hC00h bit 1514131211109 8 7654321bit 0 usb command reset0000000000000000 usb status function 2 offset 03hC02h bit 1514131211109 8 7654321bit 0 usb status reset0000000000000000 usb interrupt enable function 2 offset 05hC04h bit 1514131211109 8 7654321bit 0 usb interrupt enable reset0000000000000000 frame number function 2 offset 07hC06h bit 1514131211109 8 7654321bit 0 frame number reset0000000000000000 frame list base address function 2 offset 0bhC08h bit 1514131211109 8 7654321bit 0 usb command reset0000000000000000
registers 7-51 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information start of frame modify is an i/o register. port 1 status/control is an i/o register. port 2 status/control is an i/o register. 7.6 function 3 registers (power management) this section describes the acpi (advanced configuration and power interface) power management system of the AMD-645 peripheral bus controller. this system supports both acpi and legacy power management functions and is compatible with the apm v. 1.2 and acpi v. 0.9 specifications. 7.6.1 function 3 pci configuration space header the vendor id is a read-only register containing the value 1106h. start of frame modify function 2 offset 0ch bit 7654321bit 0 bit name start of frame modify reset00000000 port 1 status/control function 2 offset 11hC10h bit 1514131211109 8 7654321bit 0 port 1 status/control reset0000000000000000 port 2 status/control function 2 offset 13hC12h bit 1514131211109 8 7654321bit 0 port 2 status/control reset0000000000000000 vendor id function 3 offset 01hC00h ro bit 1514131211109 8 7654321bit 0 vendor id reset0001000100000110
7-52 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information the device id is a read-only register containing the value 3040h. bits 15C8 reserved (always reads zero) bit 7 reserved (address stepping - fixed at 0) bit 6 reserved (parity error response - fixed at 0) bit 5 reserved (vga pallette snoop - fixed at 0) bit 4 reserved (memory write & invalidate - fixed at 0) bit 3 reserved (special cycle monitoring - fixed at 0) bit 2 reserved (bus master - fixed at 0) bit 1 reserved (memory space - fixed at 0) bit 0 i/o space set this bit to allow access to the power management i/o register block (see offset 23hC20h on page 7-34 to set the base address for this register block). 1 = enabled 0 = disabled (default) bit 15 reserved (detected parity error - always reads 0) bit 14 reserved (signalled system error - always reads 0) bit 13 reserved (received master abort - always reads 0) bit 12 reserved (received target abort - always reads 0) bit 11 reserved (signalled target abort - always reads 0) device id function 3 offset 03hC02h ro bit 1514131211109 8 7654321bit 0 value 3040h reset0011000001000000 command function 3 offset 05hC04h rw bit 1514131211109 8 7654321bit 0 reserved ios reset0000000000000000 status function 3 offset 07hC06h rwc bit 1514131211109 8 7654321bit 0 reserved devsel# reserved reset0000001010000000
registers 7-53 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 10C9 devsel# timing 00 = fast 01 = medium (default) 10 = slow 11 = reserved bit 8 reserved (data parity detected - always reads 0) bit 7 reserved (fast back-to-back - always reads 1) bits 6C0 reserved (always reads 0) revision id is a read-only register containing the silicon revision code, where the value 00h indicates first silicon. the register defaults to the value of current silicon. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 61h. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 62h. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 63h. revision id function 3 offset 08h ro bit 7654321bit 0 bit name silicon revision code reset programming interface function 3 offset 09h ro bit 7654321bit 0 bit name 00h reset00000000 sub class code function 3 offset 0ah ro bit 7654321bit 0 bit name 03h reset00000011 base class code function 3 offset 0bh ro bit 7654321bit 0 bit name 0ch reset00001100
7-54 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information latency timer is a read-write register containing the default 16h. header type is a read-only register containing the value 00h. bits 31C16 reserved (always reads 0) bits 15C8 usb i/o register base address these two bits determine the port address for the base of the 256-byte power management i/o register block, corresponding to ad15Cad8. the i/o space bit at offset 5hC4h bit 0 enables access to this register block. bits 7C0 fixed (value of these bits is set at 00000001 binary) 7.6.2 power management-specific configuration registers bit 7 gpio4 configuration 0 = define pin 136 as gpo_we 1 = define pin 136 as gpio4 (default) latency timer function 3 offset 0dh rw bit 7654321bit 0 bit name 16h reset00010110 header type function 3 offset 0eh ro bit 7654321bit 0 bit name 00h reset00000000 power management i/o register base address function 3 offset 23hC20h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 power management i/o register base address fixed reset0000000000000001 pin configuration function 3 offset 40h rw bit 7654321bit 0 bit name gpio4 gpio3 reserved reset11000000
registers 7-55 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 6 gpio3 configuration 0 = define pin 92 as gpi_re# 1 = define pin 92 as gpio3 (default) bits 5C0 reserved (always reads 0) bit 7 pwrbtn# input debounce 0 = disable (default) 1 = enable bit 6 acpi timer reset 0 = disable (default) 1 = enable bits 5C4 reserved (do not program) bit 3 acpi timer count select 0 = 24-bit timer (default) 1 = 32-bit timer bit 2 pci frame activation in c2 as resume event 0 = disable (default) 1 = enable bit 1 clock throttling clock selection 0= 32 sec (512 sec cycle time) (default) 1 = 1 msec (16 msec cycle time) bit 0 reserved (do not program) bits 7C4 reserved (always reads 0) bits 3C10 sci interrupt assignment 0000 = disabled (default) 1000 = irq8 0001 = irq1 1001 = irq9 0010 = reserved 1010 = irq10 0011 = irq3 1011 = irq11 0100 = irq4 1100 = irq12 0101 = irq5 1101 = irq13 0110 = irq6 1110 = irq14 0111 = irq7 1111 = irq15 general configuration function 3 offset 41h rw bit 7654321bit 0 bit name pid atr reserved atcs pfa ctcs reserved reset00000000 sci interrupt configuration function 3 offset 42h rw bit 7654321bit 0 bit name reserved sci interrupt assignment reset00000000
7-56 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information setting any bit except bit 2 enables the corresponding irq as the primary interrupt channel. setting any bit except bit 2 enables the corresponding irq as the secondary interrupt channel. bits 31C30 conserve mode timer count value 00 = 1/16 sec(default) 01 = 1/8 sec 10 = 1 sec 11 = 1 minute bit 29 conserve mode status this bit reads 1 when the system is in conserve mode. bit 28 conserve mode enable set this bit to enable conserve mode (not used in desktop applications). bits 27C26 secondary event timer count value 00 = 2 msec (default) 01 = 64 msec 10 = 1/2 sec 11 = by eoi + 0.25 msec bit 25 secondary event occurred status this bit is set when a secondary event has occurred (to resume the system from suspend) and that the secondary event timer is counting down. primary interrupt channel function 3 offset 45hC44h rw bit 1514131211109 8 7654321bit 0 15p 14p 13p 12p 11p 10p 9p 8p 7p 6p 5p 4p 3p rsvd 1p 0p reset0000000000000000 secondary interrupt channel function 3 offset 47hC46h rw bit 1514131211109 8 7654321bit 0 15s14s1312s11s10s9s8s7s6s5s4s3srsvd1s0s reset0000000000000000 gp timer control function 3 offset 53hC50h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 cmtcv cms cme setcv seos sete gp1 timer count value reset0000000000000000 bit 1514131211109 8 7654321bit 0 gp0 timer count value 1ts 1ar gp1tb 0ts 0ar gp0tb reset0000000000000001
registers 7-57 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 24 secondary event timer enable 0 = disable (default) 1 = enable bits 23C16 gp1 timer count value (base defined by bits 5C4) bits 15C8 gp0 timer count value (base defined by bits 1C0) bit 7 gp1 timer start when this bit is set, the gp1 timer loads the value defined by bits 23C16 of this register and starts counting down. the gp1 timer is reloaded at the occurrence of certain peripheral events enabled in the gp timer reload enable register in function 3 i/o space, offset 38h (see page 7-69). if no such event occurs and the gp1 timer counts down to zero, then the gp1 timer timeout status bit is set. this bit is located at function 3 i/o space, offset 28h, bit 3 (see page 7-65). in addition, an smi is generated if the gp1 timer timeout enable bit is set. this bit is located at function 3 i/o space, offset 2ah, bit 3(see page 7-66). bit 6 gp1 timer automatic reload setting this bit enables the gp1 timer to reload automatically after counting down to 0. bits 5C4 gp1 timer base 00 = disable (default) 01= 32 sec 10=1 second 11=1 minute bit 3 gp0 timer start when this bit is set, the gp0 timer loads the value defined by bits 15C8 of this register and starts counting down. the gp0 timer is reloaded at the occurrence of certain peripheral events enabled in the gp timer reload enable register in function 3 i/o space, offset 38h (see page 7-69). if no such event occurs and the gp0 timer counts down to zero, then the gp0 timer timeout status bit is set. this bit is located at function 3 i/o space, offset 28h, bit 2 (see page 7-65). in addition, an smi is generated if the gp0 timer timeout enable bit is set. this bit is located at function 3 i/o space, offset 2ah, bit 2 (see page 7-66). bit 2 gp0 timer automatic reload setting this bit enables the gp0 timer to reload automatically after counting down to 0. bits 1C0 gp0 timer base 00 = disable (default) 01=1/16 second 10=1 second 11=1 minute
7-58 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bits 7C0 offset 09h read value the value returned by the register at offset 09h (programming interface) can be changed by writing the desired value to this location. bits 7C0 offset 0ah read value the value returned by the register at offset 0ah (sub class code) can be changed by writing the desired value to this location. bits 7C0 offset 0bh read value the value returned by the register at offset 0bh (base class code) can be changed by writing the desired value to this location. 7.6.3 power management i/o space registers basic power management control status the bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position. programming interface read value function 3 offset 61h wo bit 7654321bit 0 bit name offset 09h read value reset00000000 sub class read value function 3 offset 62h wo bit 7654321bit 0 bit name offset 0ah read value reset00000000 base class read value function 3 offset 63h wo bit 7654321bit 0 bit name offset 0bh read value reset00000000 power management status offset 01hC00h rwc bit 1514131211109 8 7654321bit 0 ws reserved pbos rtcs rsvd pbs reserved gs bms reserved tcs reset0000000000000000
registers 7-59 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 15 wakeup status (wak_sts) (default = 0) this bit is set when the system is in the suspend state and an enabled resume event occurs. upon setting this bit, the system automatically transitions from the suspend state to the normal working state (from c3 to c0 for the processor). bits 14C12 reserved (always reads 0) bit 11 power button override status (pbor_sts) (default = 0) this bit is set when the pwrbtn# input pin is continuously asserted for more than 4 seconds. the setting of this bit will reset the pb_sts bit and transition the system into the soft off state. bit 10 rtc status (rtc_sts) (default = 0)this bit is set when the rtc generates an alarm in response to assertion of the rtc irq signal. bit 9 reserved (always reads 0) bit 8 power button status (pb_sts) (default = 0)this bit is set when the pwrbtn# signal is asserted low. if the pwrbtn# signal is held low for more than four seconds, this bit is cleared, the pbor_sts bit is set, and the system transitions into the soft off state. bit 7C6 reserved (always reads 0) bit 5 global status (gbl_sts) (default = 0) this bit is set by hardware when bios_rls is set (typically by an smi routine to release control of the sci/smi lock). when this bit is cleared by software (by writing a one to this bit position) the bios_rls bit is simultaneously cleared by hardware. bit 4 bus master status (bm_sts) (default = 0)this bit is set when any system bus master requests the system bus, including all pci master, isa master and isa dma devices. bits 3C1 reserved (always reads 0) bit 0 timer carry status (tmr_sts) (default = 0) this bit is set when the 23rd (31st) bit of the 24 (32) bit acpi power management timer changes. the bits in this register correspond to the bits in the power management status register at function 3, offset01hC00h. bit 15C11 reserved (always reads 0) bit 10 rtc enable (rtc_en) (default = 0) this bit can be set to trigger either an sci or an smi (depending on the setting of the sci_en bit) to be generated when the rtc_sts bit is set. bit 9 reserved (always reads 0) power management enable offset 3hC2h rw bit 1514131211109 8 7654321bit 0 reserved rtce rsvd pbe reserved ge reserved ate reset0000000000000000
7-60 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 8 power button enable (pb_en) (default = 0) this bit can be set to trigger either an sci or an smi (depending on the setting of the sci_en bit) to be generated when the pb_sts bit is set. bits 7C6 reserved (always reads 0) bit 5 global enable (gbl_en) (default = 0) this bit can be set to trigger either an sci or an smi (depending on the setting of the sci_en bit) to be generated when the gbl_sts bit is set. bits 4C1 reserved (always reads 0) bit 0 acpi timer enable (tmr_en) (default = 0) this bit can be set to trigger either an sci or an smi (depending on the setting of the sci_en bit) to be generated when the tmr_sts bit is set. bits 15C14 reserved (always reads 0) bit 13 sleep enable (slp_en) (always reads 0) this is a write-only bit. reads from this bit always return zero. writing a one to this bit causes the system to sequence into the sleep (suspend) state defined by the slp_typ field, bits 12C10. bits 12C10 sleep type (slp_typ) 000 = soft off (also called suspend to disk). the v dd5 power plane is turned off while the v dd -5vsb and v dd -rtc (vbat) planes remain on. 010 = power on suspend. all power planes remain on but the processor is put into the c3 state. 0x1 = reserved 1xx = reserved note: to facilitate hardware design, minimal interface exists between powered and non-powered planes in either sleep state. bits 9C3 reserved (always reads 0) bit 2 global release (gbl_rls) (default = 0) this bit is set by acpi software to indicate the release of the sci/smi lock. when this bit is set, hardware automatically sets the bios_sts bit. gbl_rls is cleared by hardware when the bios_sts bit is cleared by software. note that setting this bit will generate an smi if the bios_en bit is set (bit 5 of the global enable register at offset 2ah). bit 1 bus master reload (bms_rld) (default = 0)this bit is used to enable the occurrence of a bus master request to transition the processor from the c3 state to the c0 state. power management control offset 05hC04h rw bit 1514131211109 8 7654321bit 0 reserved se sleep type reserved gr bmr scie reset0 0 0 0 0oooooo 00000
registers 7-61 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 0 sci enable (sci_en) this bit determines whether a power management event generates an sci or smi. 0 = generate smi (default) 1 = generate sci note: certain power management events can be programmed individually to generate an sci or smi independent of the setting of this bit. refer to the general purpose sci enable and general purpose smi enable registers at function 3, offsets 22h and 24h, on page 7-63. also, tmr_sts & gbl_sts always generate an sci and bios_sts always generates an smi. bits 31C24 extended timer value (etm_val) this field reads back 0 if the 24-bit timer option is selected in configuration register function 3, offset 41h, bit 3 (see page 7-55). bits 23C0 timer value (tmr_val) this read-only field returns the running count of the power management timer. this timer is a 24-/32-bit counter driven by a 3.579545-mhz clock derived from an external 14.31818-mhz input when the system is in the s0 (working) state. the timer is reinitialized to zero during a reset and continues counting until the 14.31818 mhz input to the chip is stopped. the clock retains its value when the external timing source is stopped, and continues to count from that value when the clock is restarted without a reset. processor power management registers bits 31C5 reserved (always reads 0) power management timer offset 0bhC08h rw bits 31C24 bits 23C0 bit name extended timer value timer value reset 0 0 processor control offset 13h-10h rw bits 31C5 bit 4 bits 3C1 bit 0 bit name reserved te tdc reserved reset 0 000
7-62 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 4 throttling enable (tht_en) this bit determines the effect of reading the p_lvl2 port 0 =reading the p_lvl2 port asserts stpclk# and suspends the processor 1 = reading the p_lvl2 port enables clock throttling by modulating the stpclk# signal with a duty cycle determined by bits 3C1 of this register. bits 3C1 throttling duty cycle (tht_dty) this 3-bit field determines the duty cycle of the stpclk signal when the system is in throttling mode (i.e., tht_en is set to one and the register p_lvl2 is read). the duty cycle indicates the percentage of time the stpclk signal is asserted while the tht_en bit is set. the field is decoded as follows: 000 = reserved 001 = 0-12.5% 010 = 12.5-25% 011 = 25-37.5% 100 = 37.5-50% 101 = 50-62.5% 110 = 62.5-75% 111 = 75-87.5% bit 0 reserved (always reads 0) bits 7C0 lvl2 (always reads 0) reads from this register put the processor in the c2 clock state determined by the tht_en bit. reads from this register return all zeros; writes to this register have no effect. bits 7C0 lvl3 (always reads 0) reads from this register put the processor in the c3 clock state with the stpclk# signal asserted. reads from this register return all zeros. writes to this register have no effect. processor level 2 (p_lvl2) offset 14h ro bit 7654321bit 0 bit name processor level 2 reset00000000 processor level 3 (p_lvl3) offset 15h ro bit 7654321bit 0 bit name processor level 3 reset00000000
registers 7-63 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information general purpose power management registers bits 15C10 reserved (always reads 0) bit 9 usb resume status (usb_sts) this bit is set when a usb peripheral generates a resume event. bit 8 ring status (ri_sts) this bit is set when the ri# input is asserted low. bit 7 extsmi7 toggle status (ext7_sts) this bit is set when the extsmi7# pin is toggled. bit 6 extsmi6 toggle status (ext6_sts) this bit is set when the extsmi6# pin is toggled. bit 5 extsmi5 toggle status (ext5_sts) this bit is set when the extsmi5# pin is toggled. bit 4 extsmi4 toggle status (ext4_sts) this bit is set when the extsmi4# pin is toggled. bit 3 extsmi3 toggle status (ext3_sts) this bit is set when the extsmi3# pin is toggled. bit 2 extsmi2 toggle status (ext2_sts) this bit is set when the extsmi2# pin is toggled. bit 1 extsmi1 toggle status (ext1_sts) this bit is set when the extsmi1# pin is toggled. bit 0 extsmi0 toggle status (ext0_sts) this bit is set when the extsmi0# pin is toggled. note: bits 9C0 correspond one-for-one with the bits of the general purpose sci enable (offset 23hC22h) and general purpose smi enable registers (offset 25hC24h). an sci or smi is generated if the corresponding bit of the general purpose sci or smi enable registers, respectively, is set. bits 9C0 are set only by hardware and can be cleared only by writing a one to the desired bit. bit 15C10 reserved (always reads 0) bit 9 enable sci on setting of the usb_sts bit (default = 0) general purpose status (gp_sts) offset 21hC20h rwc bit 1514131211109 8 7654321bit 0 reserved usbs rs es7 es6 es5 es4 es3 es2 es1 es0 reset0 0 0 0 0ooooo 000000 general purpose sci enable offset 23hC22h rw bit 1514131211109 8 7654321bit 0 reserved eusberie7e6e5e4e3e2e1e0 reset0000000000000000
7-64 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 8 enable sci on setting of the ri_sts bit (default = 0) bit 7 enable sci on setting of the ext7_sts bit (default = 0) bit 6 enable sci on setting of the ext6_sts bit (default = 0) bit 5 enable sci on setting of the ext5_sts bit (default = 0) bit 4 enable sci on setting of the ext4_sts bit (default = 0) bit 3 enable sci on setting of the ext3_sts bit (default = 0) bit 2 enable sci on setting of the ext2_sts bit (default = 0) bit 1 enable sci on setting of the ext1_sts bit (default = 0) bit 0 enable sci on setting of the ext0_sts bit (default = 0) these bits allow generation of an sci using a separate set of conditions from those used for generating an smi. bit 15C10 reserved (always reads 0) bit 9 enable smi on setting of the usb_sts bit (default = 0) bit 8 enable smi on setting of the ri_sts bit (default = 0) bit 7 enable smi on setting of the ext7_sts bit (default = 0) bit 6 enable smi on setting of the ext6_sts bit (default = 0) bit 5 enable smi on setting of the ext5_sts bit (default = 0) bit 4 enable smi on setting of the ext4_sts bit (default = 0) bit 3 enable smi on setting of the ext3_sts bit (default = 0) bit 2 enable smi on setting of the ext2_sts bit (default = 0) bit 1 enable smi on setting of the ext1_sts bit (default = 0) bit 0 enable smi on setting of the ext0_sts bit (default = 0) these bits allow generation of an smi using a separate set of conditions from those used for generating an sci. bit 15C11 reserved (always reads 0) bit10 ring ps control (ri_ps_ctl) (default = 0) this bit enables setting the ri_sts bit to turn on the v dd _5v power plane by setting pwron = 1. general purpose smi enable offset 25hC24h rw bit 1514131211109 8 7654321bit 0 reserved eusberie7e6e5e4e3e2e1e0 reset0000000000000000 power supply control offset 27hC26h rw bit 1514131211109 8 7654321bit 0 reserved rpsc pbc rsc reserved es0 reset0000000000000000
registers 7-65 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 9 power button control (pb_ctl) (default = 0) this bit is used to set the pb_sts bit to resume the system from suspend (turn on the v dd _5v power plane by setting pwron = 1). bit 8 rtc ps control (rtc_ps_ctl) (default = 0)this bit enables setting the rtc_sts bit to resume the system from suspend (turn on the v dd _5v power plane by setting pwron = 1). bit 7C1 reserved (always reads 0) bit 0 extsmi0 toggle ps control (e0_ps_ctl) (default = 0) this bit enables the setting of the ext0_sts bit to resume the system from suspend (turn on the v dd _5v power plane by setting pwron = 1). generic power management registers bit 15C7 reserved (always reads 0) bit 6 software smi status (sw_smi_sts) (default = 0) this bit is set when the smi_cmd port (offset 2fh) is written. bit 5 bios status (bios_sts) (default = 0)this bit is set when the gbl_rls bit is set (typically by the acpi software to release control of the sci/smi lock). when this bit is reset (by writing a one to this bit position) the gbl_rls bit is reset at the same time by hardware. bit 4 legacy usb status (leg_usb_sts) (default = 0)this bit is set when a legacy usb event occurs. bit 3 gp1 timer time out status (gp1to_sts) (default = 0)this bit is set when the gp1 timer times out. bit 2 gp0 timer time out status (gp0to_sts) (default = 0)this bit is set when the gp0 timer times out. bit 1 secondary event timer time out status (stto_sts) (default = 0)this bit is set when the secondary event timer times out. bit 0 primary activity status (pact_sts) (default = 0)this bit is set at the occurrence of any enabled primary system activity (see the primary activity detect status register at offset 30h, page 7-67, and the primary activity detect enable register at offset 34h, page 7-68). after checking this bit, software can check the status bits in the primary activity detect status register at offset 30h to identify the specific source of the primary event. setting this bit can be enabled to reload the gp0 timer (see bit 0 of the gp timer reload enable register at offset 38h, page 7-69). note that global status offset 29hC28h rwc bit 1514131211109 8 7654321bit 0 reserved sss bs lus g1ts g2ts seto pas reset0000000000000000
7-66 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information an smi can be generated based on the setting of any of the above bits (see the bit descriptions of the global enable register, offset 2ah, page 7-66). the bits in this register are set only by hardware and can be cleared only by writing a one to the desired bit position. bit 15C7 reserved (always reads 0) bit 6 software smi enable (sw_smi_en) (default = 0) this bit can be set to trigger an smi when the sw_smi_sts bit is set. bit 5 bios enable (bios_en) (default = 0)this bit can be set to trigger an smi when the bios_sts bit is set. bit 4 legacy usb enable (leg_usb_en) (default = 0)this bit can be set to trigger an smi when the leg_usb_sts bit is set. bit 3 gp1 timer time out enable (gp1to_en) (default = 0)this bit can be set to trigger an smi when the gp1to_sts bit is set. bit 2 gp0 timer time out enable (gp0to_en) (default = 0)this bit can be set to trigger an smi when the gp0to_sts bit is set. bit 1 secondary event timer time out enable (stto_en) (default = 0) this bit can be set to trigger an smi when the stto_sts bit is set. bit 0 primary activity enable (pact_en) (default = 0)this bit can be set to trigger an smi when the pact_sts bit is set. bit 15C9 reserved (always reads 0) bit 8 smi active (insmi) 0 = smi inactive (default) 1 = smi active. if bit 4 (smiig) is set, bit 8 must be cleared by writing a 1 to it before the next smi can be generated. bit 7C5 reserved (always reads 0) bit 4 smi lock (smiig) (rwc) 0 = disable smi lock (default) 1 = enable smi lock (smi low to gate for the next smi) bit 3 reserved (always reads 0) global enable offset 2bhC2ah rw bit 1514131211109 8 7654321bit 0 reserved sse be lue g1e g0e sete pae reset0000000000000000 global control (gbl_ctl) offset 2dhC2ch rw bit 1514131211109 8 7654321bit 0 reserved sa reserved smil rsvd bpt br smie reset0000000000000000
registers 7-67 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 2 power button triggering set this bit to prevent the situation in which pb_sts is set to wake up the system, then reset by pbor_sts to switch the system into the soft-off state. bit 2 must be cleared to comply with acpi v. 0.9. 0 = sci/smi generated by pwrbtn# low level 1 = sci/smi generated by pwrbtn rising edge bit 1 bios release (bios_rls) this bit is set by legacy software to indicate release of the sci/smi lock. upon setting of this bit, hardware automatically sets the gbl_sts bit. this bit is cleared by hardware when the gbl_sts bit cleared by software. note: if the gbl_en bit is set (bit 5 of the power management enable register at offset 2h), then setting this bit causes an sci to be generated (because setting this bit causes the gbl_sts bit to be set). bit 0 smi enable (smi_en) 0 = disable all smi generation 1 = enable smi generation bit 7C0 smi command writing to this port sets the sw_smi_sts bit. note that if the sw_smi_en bit is set (see bit 6 of the global enable register at offset 2ah), then an smi is generated. these bits correspond to the primary activity detect enable bits in offset 37hC34h. bit 31C8 reserved (always reads 0) bit 7 keyboard controller access status (kbc_sts) set if the keyboard controller is accessed via i/o port 60h. bit 6 serial port access status (ser_sts) set if the serial port is accessed via i/o ports 3f8hC3ffh, 2f8hC2ffh, 3e8hC3efh, or 2e8hC2efh (com1C4, respectively). smi command (smi_cmd) offset 2fh rw bit 7654321bit 0 bit name smi command reset00000000 primary activity detect status offset 33hC30h rwc bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 reserved kcas spas ppas vas ifas rsvd pias idas reset0000000000000000
7-68 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 5 parallel port access status (par_sts) set if the parallel port is accessed via i/o ports 278hC27fh or 378hC37fh (lpt2 or lpt1). bit 4 video access status (vid_sts) set if the parallel port is accessed via i/o ports 278hC27fh or 378hC37fh (lpt2 or lpt1). bit 3 ide / floppy access status (ide_sts) set if the parallel port is accessed via i/o ports 278hC27fh or 378hC37fh (lpt2 or lpt1). bit 2 reserved (always reads 0) bit 1 primary interrupt activity status (pirq_sts) this bit is set when a primary interrupt occurs. primary interrupts are enabled in the primary interrupt channel register at function 3, pci configuration register offset 44h (see page 7-56). bit 0 isa master / dma activity status (drq_sts) this bit is set by isa master or dma activity. the bits in this register correspond to the bits in the primary activity detect enable register at offset 34h (page 7-67). if the corresponding bit is set in that register, setting the bit in this register will cause the pact_sts bit to be set (bit 0 of the global status register at offset 28h, page 7-65). setting of pact_sts can be set up to enable a "primary activity event", where an smi will be generated if pact_en is set (bit 0 of the global enable register at offset 2ah, page 7-66) and/or the gp0 timer will be reloaded if the gp0 timer reload on primary activity bit is set (bit 0 of the gp timer reload enable register at offset 38h, page 7-69). bits 3C7 in this register also correspond to bits 3C7 of the gp timer reload enable register at offset 38h. if the corresponding bit is set in that register, setting the bit in this register will cause the gp1 timer to be reloaded. all bits of this register are set only by hardware and can be cleared only by writing a one to the desired bit. all bits default to 0. these bits correspond to the primary activity detect status bits in offset 33hC30h. bit 31C8 reserved (always reads 0) primary activity detect enable offset 37hC34h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 reserved kcse spse ppse vse ifse rsvd pise idse reset0000000000000000
registers 7-69 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 7 keyboard controller status enable (kbc_en) 0 = don't set pact_sts if kbc_sts is set (default) 1 = set pact_sts if kbc_sts is set bit 6 serial port status enable (ser_en) 0 = don't set pact_sts if ser_sts is set (default) 1 = set pact_sts if ser_sts is set bit 5 parallel port status enable (par_en) 0 = don't set pact_sts if par_sts is set (default) 1 = set pact_sts if par_sts is set bit 4 video status enable (vid_en) 0 = don't set pact_sts if vid_sts is set (default) 1 = set pact_sts if vid_sts is set bit 3 ide / floppy status enable (ide_en) 0 = don't set pact_sts if ide_sts is set (default) 1 = set pact_sts if ide_sts is set bit 2 reserved (always reads 0) bit 1 primary intr status enable (pirq_en) 0 = don't set pact_sts if pirq_sts is set (default) 1 = set pact_sts if pirq_sts is set bit 0 isa master / dma status enable (drq_en) 0 = don't set pact_sts if drq_sts is set (default) 1 = set pact_sts if drq_sts is set note: setting any of bits 7C0 also sets the pact_sts bit (bit 0 of offset 28h), which reloads the gp0 timer (if pact_gp0_en is set) or generates an smi (if pact_en is set). all bits in this register default to 0 on power up. bit 31C8 reserved (always reads 0) bit 7 enable gp1 timer reload on kbc access 1 = setting kbc_sts causes gp1 timer to reload bit 6 enable gp1 timer reload on serial port access 1 = setting ser_sts causes gp1 timer to reload gp timer reload enable offset 3bhC38h rw bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit 16 reserved reset0000000000000000 bit 1514131211109 8 7654321bit 0 reserved e1ka k1sa rsvd e1va e1ia reserved idse reset0000000000000000
7-70 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 5 reserved (always reads 0) bit 4 enable gp1 timer reload on video access 1 = setting vid_sts causes gp1 timer to reload bit 3 enable gp1 timer reload on ide/floppy access 1 = setting ide_sts causes gp1 timer to reload bit 2C1 reserved (always reads 0) bit 0 enable gp0 timer reload on primary activity 1 = setting pact_sts causes gp0 timer to reload. primary activities are enabled via the primary activity detect enable register (offset 37hC34h) with status recorded in the primary activity detect status register (offset 33hC30h). general purpose i/o registers bit 7C5 reserved (always reads 0) bit 4 gpio4_dir 0 = pin 136 is gpio4 input (default) 1 = pin 136 is gpio4 output (if offset 40h bit 7 = 1) if offset 40h bit 7 = 0 (pci configuration function 3 offset 40h gpio4_cfg bit), pin 136 is the gpo_we output, independent of the state of this bit. bit 3 gpio3_dir 0 = pin 92 is gpio3 input (default) 1 = pin 92 is gpio3 output (if offset 40h bit 6 = 1) if offset 40h bit 6 = 0 (pci configuration function 3 offset 40h gpio3_cfg bit), pin 92 is the gpi_re# output, independent of the state of this bit. bit 2 gpio2_dir 0 = pin 88 is gpio2 / i2cd1 input (default) 1 = pin 88 is gpio2 / i2cd1 output bit 1 gpio1_dir 0 = pin 87 is gpio1 / i2cd2 input (default) 1 = pin 87 is gpio1 / i2cd2 output gpio direction control (gpio_dir) offset 40h rw bit 7654321bit 0 bit name reserved g4d g3d g2d g1d g0d reset00000000
registers 7-71 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information bit 0 gpio0_dir 0 = pin 94 is gpio0 input (default) 1 = pin 94 is gpio0 output bit 7C5 reserved (always reads 0) bit 4 gpio4_val write output value for the gpio4 pin if the port is available (gpio4_cfg = 1 in pci configuration register function 3, offset 40h). the input state of the gpio4 pin can be read from register extsmi_val bit 4. bit 3 gpio3_val write output value for the gpio3 pin if the port is available (gpio3_cfg = 1 in pci configuration register function 3, offset 40h). the input state of the gpio3 pin can be read from register extsmi_val bit 3. bit 2 gpio2_val write output value for the gpio2 (i2cd2) pin. the input state of the gpio2 pin can be read from register extsmi_val bit 2. bit 1 gpio1_val write output value for the gpio1 (i2cd1) pin. the input state of the gpio1 pin can be read from register extsmi_val bit 1. bit 0 gpio0_val write output value for the gpio0 pin. the input state of the gpio0 pin can be read from register extsmi_val bit 0. depending on the configuration, up to eight external sci/smi ports are available as indicated below. the state of inputs extsmi7#Cextsmi0# can be read in this register. bit 7 extsmi7# input value gpio3_cfg = 0: extsmi7# on xd7 (pin 122) gpio3_cfg = 1: extsmi7# function not available bit 6 extsmi6# input value gpio3_cfg = 0: extsmi6# on xd6 (pin 121) gpio3_cfg = 1: extsmi6# function not available bit 5 extsmi5# input value gpio3_cfg = 0: extsmi5# on xd5 (pin 119) gpio3_cfg = 1: extsmi5 function not available gpio port output value (gpio_val) offset 42h rw bit 7654321bit 0 bit name reserved g4v g3v g2v g1v g0v reset00000000 gpio port input value (extsmi_val) offset 44h ro bit 7654321bit 0 bit name e7iv e6iv e5iv e4iv e3iv e2iv e1iv e0iv reset00000000
7-72 registers AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information bit 4 extsmi4# input value gpio4_cfg = 0: gpio3_cfg = 0: extsmi4 on xd4 (pin 118) gpio3_cfg = 1: extsmi4 function not available gpio4_cfg = 1: extsmi4# on gpio4 (pin 136) bit 3 extsmi3# input value gpio3_cfg = 0: extsmi3# on xd3 (pin 117) gpio3_cfg = 1: extsmi3# on gpio3 (pin 92) bit 2 extsmi2# input value (on gpio2 pin 88) bit 1 extsmi1# input value (on gpio1 pin 87) bit 0 extsmi0# input value (on gpio0 pin 94) note: gpio3_cfg and gpio4_cfg are located in pci configuration register function 3, offset 40h. reads from this register return the last value written (held on chip). bit 15C8 gpo15C8 value. output port value for the external gpo port connected to sd15C8. this port is available only if the gpio4_cfg bit is cleared to define pin 136 as gpo_we. bit 7C0 gpo7C0 value. output port value for the external gpo port connected to xd7C0. this port is available only if the gpio4_cfg bit is cleared to define pin 136 as gpo_we. note: gpio4_cfg is in pci register function 3, offset 40h, page 7-54. reads from this register are ignored (and return a value of 0). bit 15-8 gpi15-8 value. input port value for the external gpi port connected to sd15-8. this port is available only if the gpio3_cfg bit is cleared to define pin 92 as gpi_re#. bit 7-0 gpi7-0 value. input port value for the external gpi port connected to xd7C xd0. this port is available only if the gpio3_cfg bit is cleared to define pin 92 as gpi_re# . note: gpio3_cfg is in pci configuration register function 3, offset 40h. gpo port output value (gpo_val) offset 47hC46h rw bit 1514131211109 8 7654321bit 0 gpo15C8 value gpo7C0 value reset0000000000000000 gpi port input value (gpi_val) offset 49hC48h ro bit 1514131211109 8 7654321bit 0 gpi15C8 value gpi7C0 value reset0000000000000000
electrical data 8-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 8 electrical data 8.1 absolute ratings long-term reliability and functional integrity of the AMD-645 peripheral bus controller are guaranteed as long as it is not subjected to conditions exceeding the absolute ratings listed in table 11 - 1. warning : stress above the parameters listed can cause permanent damage to the device. functional operation of this device should be restricted to the described conditions. table 8-1. absolute maximum ratings parameter minimum maximum unit ambient operating temperature 0 70 o c storage temperature -55 125 o c input voltage -0.5 5.5 voltage output voltage (v dd = 5 v) -0.5 5.5 voltage output voltage (v dd = 3.1 v - 3.6 v) -0.5 v dd + 0.5 voltage table 8-2. absolute ratings parameter minimum maximum comments v dd -0.5 v 5.5 v v dd3 -0.5 v 3.6 v pin -0.5 v v dd3 +0.5 v and 4.0 v note 1 t case (under bias) -65 c+110 c t storage -65 c+150 c note: 1. v pin (the voltage on any i/o pin) must not be greater than 0.5 v above the voltage being applied to v dd3 . in addition, the v pin voltage must never exceed 4.0 v.
8-2 electrical data AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 8.2 operating ranges the functional operation of the AMD-645 peripheral bus controller is guaranteed if the voltage and temperature parameters are within the limits defined in table 11-2. table 8-3. operating ranges parameter minimum typical maximum comments v dd 4.75 v 5.0 v 5.25 v (note 1) v dd3 3.135 v 3.3 v 3.465 v (note 1) t case 0 c70 c note: 1. v dd and v dd3 are referenced from v ss
electrical data 8-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 8.3 dc characteristics table 8-4. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage -0.50 v 0.8 v v ih input high voltage 2.0 v v dd +0.5 v note 1 v ol output low voltage 0.45 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 1.0-ma load i dd 5 v power supply current 33 mhz, note 2 i dd3 3.3 v power supply current 33 mhz, note 3 i li input leakage current 10 m a note 4 i lo output leakage current 20 m a note 4 i il input leakage current bias with pullup -10 m a note 5 i ih input leakage current bias with pulldown 10 m a note 6 c in input capacitance 10 pf c out output capacitance 15pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v dd3 refers to the voltage being applied to v dd3 during functional operation. 2. v dd = 5.25 v the maximum power supply current must be taken into account when designing a power supply. 3. v dd3 = 3.465 v the maximum power supply current must be taken into account when designing a power supply. 4. refers to inputs and i/o without an internal pullup resistor and 0 v in v dd3. 5. refers to inputs with an internal pullup and v il = 0.4 v. 6. refers to inputs with an internal pulldown and v ih = 2.4 v.
8-4 electrical data AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 8.4 power dissipation table 11-4 shows typical and maximum power dissipation of the AMD-645 peripheral bus controller during normal and reduced power states. the measurements are taken with pclk = 33 mhz, v dd = 5.0v and v dd 3 = 3.3v. table 8-5. typical and maximum power dissipation clock control state typical ( note 1) maximum (note 2) comments normal (thermal power) 2.3 w? 0.40 w? note 3 notes: 1. typical power is measured during instruction sequences or functions associated with normal system opera- tion. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states. 3. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the AMD-645 peripheral bus controller processor.
switching characteristics 9-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 9 switching characteristics this section summarizes the AMD-645 peripheral bus controller signal switching characteristics. valid delay, float, setup, and hold timing specifications are listed. all signal timings are based on the following conditions: n the target signals are input or output signals that are switching from logical 0 to 1, or from logical 1 to 0. n measurements are taken from the time the reference signal (cclk, pclk, or reset) passes through 1.5 v to the time the target signal passes through 1.5 v. n all signal slew rates are 1 v/ns, from 0 v to 3 v (rising) or 3 v to 0 v (falling). n parameters are within the operating range listed in table 8-1 on page 8-1. n the load capacitance (c l ) on each signal is 0 pf.
9-2 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.1 pclk switching characteristics table 9-1 contains the switching characteristics of the pclk input to the AMD-645 peripheral bus controller as measured at the voltage levels indicated by figure 9-1. the pclk period stability specifies the variance (jitter) allowed between successive periods of the clk input measured at 1.5 v. this parameter must be considered as one of the elements of clock skew between the AMD-645 peripheral bus controller and the system logic.
switching characteristics 9-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-1. pclk waveform table 9-1. clk switching characteristics for 33-mhz pci bus symbol parameter description preliminary data figure comments min max t 1 clk cycle 30 ns ? t 2 clk high time 11.0 ns 9-1 t 3 clk low time 11.0 ns 9-1 t 4 clk fall time 1 v/ns 4v/ns 9-1 t 5 clk rise time 1 v/ns 4v/ns 9-1 clk period stability 250 ps note 1 note: 1. jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz. t 2 2.0 v 1.5 v 0.8 v t 5 t 1 t 4 t 3
9-4 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-2. usbclk switching characteristics for 12-mhz usb bus symbol parameter description preliminary data figure comments min max t 1 driver jitter 3 ns t 2 receiver jitter 25 ns 9-1 t 3 output fall time 4 ns 20 ns 9-1 t 4 output rise time 4 ns 20 ns 9-1 t 5 source differential skew 5 ns 9-1 receiver differential skew 10 ns single-ended driver skew 10 ns frequency 11.97 mbps 12.03 mbps note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz. table 9-3. usbclk switching characteristics for 1.5-mhz usb bus symbol parameter description preliminary data figure comments min max t 1 driver jitter 3 ns t 2 receiver jitter 25 ns 9-1 t 3 output fall time 75 ns 300 ns 9-1 t 4 output rise time 75ns 300 ns 9-1 t 5 source differential skew 5 ns 9-1 receiver differential skew 10 ns single-ended driver skew 10 ns frequency 1.48 mbps 1.52 mbps note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz.
switching characteristics 9-5 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information table 9-4. bclk switching characteristics for 8-mhz bus symbol parameter description preliminary data figure comments min max frequency 8 mhz t 1 clock period 125 ns t 2 clock high time 49 ns 9-1 t 3 clock low time 49 ns s 9-1 t 4 clock rise time 4 ns 9-1 t 5 clock fall time 4 ns 9-1 note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz. table 9-5. osc switching characteristics for 14.3182-mhz bus symbol parameter description preliminary data figure comments min max frequency 14.3182 mhz 9-1 t 1 clock period 67 ns 70 ns 9-1 t 2 clock high time 20 ns 9-1 t 3 clock low time 20 ns s 9-1 note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz.
9-6 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.2 valid delay, float, setup, and hold timings the following valid delay and float timings for output signals during functional operation are relative to the rising edge of the given clock. the maximum valid delay timings are provided to allow a system designer to determine if setup times can be met. likewise, the minimum valid delay timings are used to analyze hold times. the setup and hold time requirements for the AMD-645 peripheral bus controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-645 peripheral bus controller. figure 9-2. setup, hold, and valid delay timing diagram t su t h t vd t vd data in data out clk
switching characteristics 9-7 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 9.3 pci interface timing table 9-6. pci interface timing symbol parameter description preliminary data figure comments min max t su ad[31:0] setup time 7 ns 9-2 preq#, req[d:a]# setup time 12 ns 9-2 setup time for frame#, stop#, trdy#, devsel#, irdy#, c/be[3:0]# 7 ns 9-2 t h ad[31:0] hold time 0 ns 9-2 hold time for frame#, stop#, trdy#, devsel#, irdy#, c/be[3:0]# 0 ns 9-2 t vd ad[31:0] valid delay (address phase) 2 ns 11 ns 9-2 pad 12 (note 1) ad[31:0] valid delay (data phase) 2 ns 11 ns 9-2 pad 12 (note 1) valid delay for frame#, stop#, trdy#, devsel#, irdy# c/be[3:0]# 2 ns 11 ns 9-2 pad 13 (note 1) pgnt# valid delay 2 ns 12 ns 9-2 t fd float delay for frame#, stop#, trdy#, devsel#, irdy# c/be[3:0]# 28 ns 9-2 (note 1) t lat preq# to pgnt# latency 2 clks clks 9-2 note: 1. measurements are taken with a 50pf load, unless otherwise noted.
9-8 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.4 isa interface timing table 9-7. isa master interface timing symbol parameter description preliminary data figure comments min max t su2a la[23:17] setup to bale 150 ns 9-3 t su2b la[23:17] setup to memx# 173 ns 9-3 t su3a sa[19:0] setup to bale 37 ns 9-3 t su3b sa[19:0] setup time to memx# 34 ns 9-3 t su9 sd[15:0] setup to memr# 24 ns 9-3 t su10 sd[15:0] setup to memw# -40 ns 9-3 t h2 bale to la[23:17] hold time 26 ns 9-3 t h3 memx# to sa[19:0]hold 41 ns 9-3 t h6 la[23:17] to memcs16# hold 0 ns 9-3 t h9 memr# to sd[15:0] hold time 0 ns 9-3 t h10 memw# to sd[15:0] hold time 45 ns 9-3 t vd1 memx# to bale valid delay 44 ns 9-3 t vd5 memx# to smemr# & smemw# 16 ns 9-3 t vd6a sa[19:0], sbhe# to memcs16# valid delay 35 ns 9-3 t vd6b la[23:17] to memcs16# valid delay 94 ns 9-3 t vd7a sa[19:0], sbhe# to zerows# delay 200 ns 9-3 t vd7b memw# to zerows# delay 16 ns 9-3 t vd8 memx# to iochrd valid delay 78 ns 9-3 t vd9 memr# to sd[15:0] valid delay 150 ns 9-3 t pw1 bale pulse width 50 ns 9-3 t pw4a memx# active pulse width 225 ns 9-3 t pw4b memx# inactive pulse width 163 ns 9-3 t pw8 iochrdy inactive pulse width 120 ns 9-3 t fd9 memr# to sd[15:0] float delay 41 ns 9-3 t fd10 memw# to sd[15:0] float delay 105 ns 9-3 note: measurements are taken with no load.
switching characteristics 9-9 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-3. isa master interface timing t pw1 t su3a t h2 t pw1 t su2b t h6 t su3b t h3b t su9 t su8 t h9 t h10 t pw4b t pw8 t vd1 t vd5 t vd6a t vd6b t vd7a t vd7b t vd8 t vd9 t fd9 t fd10 bale la[23:17] sa[19:0], sbhe# memr#, memw# smemr#, smemw# memcs16# zerows# iochrdy sd[15:0] read sd[15:0] write t pw4a t su2a
9-10 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-8. isa 8-bit slave interface timing symbol parameter description preliminary data figure comments min max t su2a aen setup to bale 111 ns 9-4 t su2b aen setup to iox# 111 ns 9-4 t su3a sa[19:0] setup to bale 37 ns 9-4 t su3b sa[19:0] setup to iox# 100 ns 9-4 t su8 sd[15:0] setup to ior# 24 ns 9-4 t su9 sd[15:0] setup to iow# -40 ns 9-4 t h2 iox# to aen hold 41 ns 9-4 t h3 iox# to sa[19:0]hold 41 ns 9-4 t h4a ior# to sd[15:0] hold 0 ns 9-4 t h4b iow# to sd[15:0] hold 45 ns 9-4 t vd1 iox# to bale valid delay 44 ns 9-4 t vd5 sa[19:0] to iocs16# valid delay 91 ns 9-4 t vd6 sa[19:0], sbhe# to zerows# valid delay 200 ns 9-4 t vd6b iow# to zerows# valid delay 80 ns 9-4 t vd7 iox# to iochrd valid delay 366 ns 9-4 t vd8 ior# to sd[15:0] valid delay 500 ns 9-4 t pw1 bale pulse width 50 ns 9-4 t pw4a iox# active pulse width 160 ns 9-4 t pw4a iox# inactive pulse width 163 ns 9-4 t pw7 iochrdy inactive pulse width 120 ns 9-4 t fd8 ior# to sd[15:0] float delay 41 ns 9-4 t fd9 iow# to sd[15:0] float delay 105 ns 9-4 note: measurements are taken with no load.
switching characteristics 9-11 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-4. isa 8-bit slave interface timing t su3b t pw1 t su2a t su3a t pw1 t su2b t h2 t h3 t pw4a t su9 t su8 t h4a t h4b t pw4b t pw7 t vd1 t vd5 t vd6a t vd6b t vd7 t vd8 t fd9 bale aen sa[19:0], sbhe# ior#, iow# iocs16# zerows# iochrdy sd[15:0] r sd[15:0] w t fd8
9-12 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-9. isa 16-bit slave interface timing symbol parameter description preliminary data figure comments min max t su2a aen setup to bale 150 ns 9-5 t su2b aen setup to iox# 150 ns 9-5 t su3a sa[19:0] setup to iox# 34 ns 9-5 t su3b sa[19:0] setup to bale 37 ns 9-5 t su7 sd[15:0] setup to ior# 24 ns 9-5 t su8 sd[15:0] setup to iow# -40 ns 9-5 t h2 iox# to aen hold 26 ns 9-5 t h3 iox# to sa[19:0] hold 41 ns 9-5 t h5 sa[19:0] to iocs16# hold 0 ns 9-5 t h7 ior# to sd[15:0] hold 0 ns 9-5 t h8 iow# to sd[15:0] hold 45 ns 9-5 t vd1 iox# to bale valid delay 44 ns 9-5 t vd5a iox# to iocs16# valid delay 16 ns 9-5 t vd5b sa[19:0] to iocs16# valid delay 35 ns 9-5 t vd6 iox# to iochrd valid delay 78 ns 9-5 t vd7 ior# to sd[15:8] valid delay 1.5 ns 8.5 ns 9-5 t pw1 bale pulse width 50 ns 9-5 t pw4a iox# active pulse width 160 ns 9-5 t pw4b iox# inactive pulse width 163 ns 9-5 t pw6 iochrdy inactive pulse width 120 ns 9-5 t fd7 ior# to sd[15:0] float delay 41 ns 9-5 t fd8 iow# to sd[15:0] float delay 105 ns 9-5 note: measurements are taken with no load.
switching characteristics 9-13 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-5. isa 16-bit slave interface timing t pw1 t su2a t su3b t pw1 t su2b t h2 t su3a t h3 t h5 t pw4a t su8 t su7 t h7 t h8 t pw4b t pw6 t vd1 t vd5a t vd5b t vd6 t vd7 t fd7 t fd8 bale aen sa[19:0],sbhe# ior#, iow# iocs16# iochrdy sd[15:0] r sd[15:0] w
9-14 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information . table 9-10. isa master-to-pci access timing symbol parameter description preliminary data figure comments min max t su2 la[23:17] setup to memx# 23 ns 9-6 t su3 sa[19:0] setup to memx# 23 ns 9-6 t su7 sd[15:0] setup to memr# ns 9-6 t su8 sd[15:0] setup to memw# -54 ns 9-6 t h2 memx# to la[23:17] hold ns 9-6 t h3 memx# to sa[19:0] hold 30 ns 9-6 t h7 memr# to sd[15:0] hold time 0 ns 9-6 t h8 memw# to sd[15:0] hold time 14 ns 9-6 t vd5 la[23:17] to memcs16# valid delay 31 ns 9-6 t vd6 memx to iochrdy valid delay 85 ns 9-6 t vd7 iochrdy to sd[15:0] valid delay 69 ns 9-6 t pw4a memx# active pulse width 214 ns 9-6 t pw4b memx# inactive pulse width 92 ns 9-6 t pw5 iochrdy inactive pulse width 120 ns 9-6 t fd7 memr# to sd[15:8] float delay 55 ns 9-6 t fd8 memw# to sd[15:8] float delay ns 9-6 note: measurements are taken with no load.
switching characteristics 9-15 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-6. isa master-to-pci access timing t su2 t h2 t su3 t h1 t pw4a t su7 t h7 t su8 t h8 t pw4b t pw6 t vd5 t vd6 t fd6 t vd7 t fd7 la[23:17] sa[19:0], sbhe# memr#, memw# memcs16# iochrdy sd[15:0] r sd[15:0] w t fd8
9-16 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information . table 9-11. other isa master timing symbol parameter description preliminary data figure comments min max t vd1 dreq to dack# valid delay 240 ns 9-7 t vd2 dack# to address, data and control valid delay 71 n s 9 -7 t fd dack# to address, data and control float delay 0 ns 9-7 note: measurements are taken with no load.
switching characteristics 9-17 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-7. other isa master timing t vd1 t fd t vd2 t fd t vd2 t fd t vd2 t fd t vd2 t fd t vd2 dreq dack# aen la[23:17] sa[15:0], sbhe# memr#, memw# ior#, iow# sd[15:0]
9-18 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.5 dma interface timing table 9-12. dma read cycle timing symbol parameter description preliminary data figure comments min max t su2 aen setup to iow# 111 ns 9-8 t su3 dack setup to iow# 312 ns 9-8 t su4 sa[19:0],la[23:17] setup to memr# 99 ns 9-8 t su6 memr# setup to iow# -26 ns 9-8 t su10 sd[15:0] setup to iow# 225 9-8 t su11 tc setup to iow# 511 9-8 t h2 iow# to aen hold 41 ns 9-8 t h3 iow# to dack# hold 155 ns 9-8 t h4 memr# to sa[19:0], la[23:17] hold 51 ns 9-8 t h6 iow# to memr# hold 40 ns 9-8 t h9 iochrdy to memr# hold 120 ns 9-8 t h10 iow# to sd[15:0] hold 36 ns 9-8 t h11 iow# to tc hold 71 ns 9-8 t vd1 iow# to drq inactive valid delay 315 ns 9-8 t vd7 memr# to smemr# valid delay 15 ns 9-8 t vd9 memr# to iochrdy valid delay 315 ns 9-8 t pw6a memr# active pulse width 495 ns 9-8 t pw6b memr# inactive pulse width 465 ns 9-8 t pw8a iow# active pulse width 495 ns 9-8 t pw8b iow# inactive pulse width 465 ns 9-8 t pw9 iochrdy inactive pulse width 125 ns 9-8 t pw11 tc active pulse width 700 ns 9-8 note: measurements are taken with no load.
switching characteristics 9-19 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-8. dma read cycle timing t su2 th2 t su3 t h3 t su4 t h4 t su4 t h4 t h4 t pw6a t su6 t pw6b t h6 t su10 t pw8a t h10 t pw8b t su11 t h11 t pw9 t pw11 t vd1 t vd7 t vd9 dreq aen dack# la[23:17] sa[19:0], sbhe# memr# smemr# iow# iochrdy sd[15:0] tc
9-20 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-13. dma write cycle timing symbol parameter description preliminary data figure comments min max t su2 aen setup to ior# 111 ns 9-9 t su3 dack# setup to ior# 73 ns 9-9 t su4 sa[19:0],la[23:17] setup to memw# 99 ns 9-9 t su10 sd[15:0] setup to ior# 9-9 t su11 tc setup to ior# 511 ns 9-9 t h2 ior# to aen hold 41 ns 9-9 t h3 ior# to dack# hold 100 ns 9-9 t h4 memw# to sa[19:0], la[23:17] hold 51 ns 9-9 t h6 ior# to memw# hold 40 ns 9-9 t h10 ior# to sd[15:0] hold 0 ns 9-9 t h11 ior# to tc hold 71 ns 9-9 t vd1 ior# to drq valid delay 558 ns 9-9 t vd6 ior# to memw# valid delay 230 ns 9-9 t vd7 memw# to smemw# valid delay 15 ns 9-9 t vd8 ior# to sd[15:0] valid delay 237 ns 9-9 t vd9 memw# to iocdry valid delay 315 ns 9-9 t pw6a memw# active pulse width 495 ns 9-9 t pw6b memw# inactive pulse width 465 ns 9-9 t pw8a ior# active pulse width 760 ns 9-9 t pw8b ior# inactive pulse width 160 ns 9-9 t pw9 iochrdy inactive pulse width 125 ns 9-9 t pw11 tc active pulse width 700 ns 9-9 note: measurements are taken with no load.
switching characteristics 9-21 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-9. dma write cycle timing t su2 t h2 t su3 t h3 t su4 t h4 t su4 t h4 t h4 t pw6a t pw6b t h6 t su10 t pw8a t h10 t pw8b t h10 t su11 t h11 t pw9 t pw11 t vd1 t vd6 t vd7 t vd9 t vd8 dreq aen dack# la[23:17] sa[19:0], sbhe# memw# smemw# ior# iochrdy sd[15:0] tc
9-22 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-14. type f dma interface timing symbol parameter description preliminary data figure comments min max t h1a iow# to dreq hold 82 ns 9-9 t h1b ior# to dreq hold 82 ns 9-9 t h3a iow# to dack hold 30 ns 9-9 t h3b ior# to dack hold 30 ns 9-9 t h10 iow# to tc hold 0 ns 9-9 t vd4a aen to iow# valid delay 111 ns 9-9 t vd4b dack# to iow# valid delay 77 ns 9-9 t vd7a aen to ior# valid delay 111 ns 9-9 t vd7b dack# to ior# valid delay 77 ns 9-9 t pw4a iow# active pulse width 110 ns 9-9 t pw4b iow# inactive pulse width 115 ns 9-9 t pw7a ior# active pulse width 110 ns 9-9 t pw7b ior# inactive pulse width 115 ns 9-9 t fd7 ior# to sd[15:8] float delay 61 ns 9-9 note: measurements are taken with no load.
switching characteristics 9-23 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-10. type f dma interface timing t h1a t h1b t h3a t h3b t pw4a t h6a t su6 t pw4b t h6a t su10 t h10 t su6 t pw7a t pw7b t h9 t h9 t pw10 t vd2 t vd4a t vd4b t vd7a t vd7b t vd9 t vd9 t fd7 dreq aen dack# iow# memr# sd[15:0] ior# memw# sd[15:0]r tc
9-24 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.6 x-bus interface timing table 9-15. x-bus interface timing symbol parameter description preliminary data figure comments min max t su7 xoe1# setup to xdir# -2 ns 8 ns 9-11 t su8 sd[15:0]r setup to memr#, ior# 24 ns 9-11 t su10 sd[15:0]w setup to memw#, iow# 24 ns 9-11 t su11 xoe# setup to xdir1# 0 ns 9-11 t h8 memr#, ior# to sd[15:0]r hold 0 ns 9-11 t h10 memw#, iow# to sd[15:0]w hold 9-11 t vd4 la[23:17], sa[19:0] to pccs# valid delay 35 ns 9-11 t vd6 memr#, ior# to xoe1# 29 ns 9-11 t vd7 memr#, ior# to xdir# valid delay 25 ns 9-11 t vd8 memr#, ior#, to sd[15:0]r valid delay 9-11 t vd10 memw#, iow# to sd[15:0]w valid delay 9-11 t vd11 memw#, iow# to xoe 29 ns 9-11 t vd12 memw#, iow# to xdir1# valid delay 25 ns 9-11 note: measurements are taken with no load.
switching characteristics 9-25 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-11. x-bus interface timing t h8 t su8 t su7 t h10 t su10 t su11 t vd4 t vd4 t vd6 t vd7 t vd8 t vd10 t vd11 t vd12 bale la[23:17] sa[19:0] pccs# memr#, ior# xoe1# xdir# sd[15:0] memw#, iow# sd[15:0] xoe# xdir1# (read) (write)
9-26 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.7 eide interface table 9-16. eide pio symbol description mode 0 mode 1 mode 2 mode 3 mode 4 t cyc cycle time (diow/r# to diow/r#) min 600 383 240 180 120 t su1 ide address setup diow/r# max 70 50 30 30 25 t pw1 8-bit diow/r# pulse width min 290 290 290 80 70 t pw1 16-bit diow/r# pulse width min 165 125 100 80 70 t rec diow/r# recovery time min CCC7025 t su2 write data setup min 60 45 30 30 20 t h2 write data hold min 30 20 15 10 10 t su3 read data setup from drive min 50 350 20 20 20 t h3 read data hold from drive min55555 t vd1 pclk to dd[15:0] valid delay min22222 t vd1 pclk to dd[15:0] valid delay max 20 20 20 20 20 t su4 dd[15:0] to pclk setup min 10 10 10 10 10 t h4 pclk to dd[15:0] hold min44444 t vd2 pclk to da[2:0] valid delay min22222 t vd2 pclk to da[2:0] valid delay max 20 20 20 20 20 t vd3 pclkc to soe#, diox#, dcsxx# valid delay min22222 t vd3 pclkc to soe#, diox#, dcsxx# valid delay max2020202020 t su5 iordy setup min 20 20 20 20 20 t h5 pclk to drdyx# hold min55555 note: all timings are in nanoseconds.
switching characteristics 9-27 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-12. eide pio t su1 t vd2 t cyc t pw1 t rec t su3 t su4 t h3 t h4 t su2 t vd1 t h2 t vd3 t vd3 t su5 t h5 pclk da[2:0], dior#, diow# dd read dd write soe# master# iordy dcsx#
9-28 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 9-17. eide dma symbol description single-word multi-word mode 0 mode 1 mode 2 mode 0 mode 1 mode 2 t cyc cycle time (dmack# to dmack#) min 960 480 240 480 150 120 t vd1 dmack# to dmarq valid delay max 200 100 80 35 t pw1 diow/r# pulse width min 480 240 120 215 80 70 t pw2 dior# deasserted pulse width min C C C 50 50 25 t pw3 diow# deasserted pulse width min C C C 215 50 25 t h1 dior# data hold time min 555555 t su1 diow# data setup time min 250 100 35 100 30 20 t su2 dmack# to diow/r# setup min000000 t h2 diow# data hold min 555555 t su2 dmack# to diow/r# min000000 t h3 diow/r# to dmack# hold min 0 0 0 20 5 5 t vd3 dior# to dmarq valid delay min 120 40 35 t vd4 diow# to dmarq valid delay 40 40 35 t vd5 pclk to dd[15:0] valid delay min222222 t vd5 pclk to dd[15:0] valid delay max 20 20 20 20 20 20 t su4 dd[15:0] to pclk setup min 10 10 10 10 10 10 t h4 pclk to dd[15:0] hold min444444 t vd7 pclkc to soe#, diox#, dcsxx# valid delay min222222 t vd7 pclkc to soe#, diox#, dcsxx# valid delay max202020202020 t su5 ddrqx to pclk min101010101010 t h5 pclk to ddrqx hold min222222 t vd8 ddackx to pclk valid delay min222222 t vd8 ddackx to pclk valid delay min 20 20 20 20 20 20 note: all timings are in nanoseconds.
switching characteristics 9-29 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information figure 9-13. eide dma t vd7 t vd1 t su5 t h5 t cyc t vd8 t pw1 t su2 t vd3 t pw2 t h3 t vd2 t su4 t vd6 t h4 t h1 t pw1 t su2 t vd4 t wp3 t h3 t su1 t vd5 t h2 pclk master#, soe# ddrq ddack# dior# dd read diow# dd write
9-30 switching characteristics AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 9.8 ultra dma-33 ide bus interface timing table 9-18. ultradma-33 ide bus interface timing symbol parameter description preliminary data figure comments min max t env1 envelope time for read initial 20 ns 70 ns 5-20 t ds1 data setup time for read initial 34 ns 5-20 t dh1 data hold time for read initial (rise) 6 ns 5-20 t env2 envelope time for write initial (rise) 20 ns 70 ns 5-24 t dvs2 data setup time for write initial (fall) 34 ns 5-24 t dvh2 data hold time for write initial (fall) 6 ns 5-24 t dvs2 data setup time for write initial 34 ns 5-24 t dvh2 data hold time for write initial 6 ns 5-24 t rfs ready to final strobe time 50 ns 5-21 t rp ready to pause time 100 ns 5-21 t li4 limited interlock time (to stop) 0 ns 150 ns 5-22 t li4 limited interlock time (to host dmardy) 0 ns 150 ns 5-22 t za4 delay time required for output drives turning on 20 ns 5-22 t dvs4 data setup time for read terminating 34 ns 5-22 t dvh4 data hold time for read terminating 6 ns 5-22 t li5 limited interlock time (to stop) 0 ns 150 ns 5-25 t li5 limited interlock time (to host strobe) 0 ns 150 ns 5-25 t mli5 limited interlock time with minimum 20 ns 5-25 t dvs5 data setup time for write terminating 34 ns 5-25 t dvh5 data hold time for write terminating 6 ns 5-25 t mli6 limited interlock time with minimum 20 ns 5-23 t za6 delay time required for output drives turning on 34 ns 5-25 t li5 limited interlock time 0 ns 150 ns 5-27 t 2 delay time of pclk to dcs3#, dcs1# 2 ns 20 ns 5-27 t 3 delay time of pclk to da2-da0 2 ns 20 ns 5-27 t 4 delay time of pclk to diow# 2 ns 20 ns 5-27 t 5 delay time of pclk to dior# 2 ns 20 ns 5-27 t wds data setup time during pio and dma write 30 ns 5-27 t wdh data hold time during pio and dma write 20 ns 5-27 t rds data setup time during pio and dma read 30 ns 5-27 t rdh data hold time during pio and dma read 20 ns 5-27
ibis models 10-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 10 ibis models all of the AMD-645 peripheral bus controllers inputs, outputs, and bidirectional buffers are implemented using a 3.3- v buffer design. in addition, a subset of the controllers i/o buffers includes a second, higher drive strength option. amd has developed several i/o buffer models that represent the characteristics of each of the possible drive strength configurations supported by the AMD-645 peripheral bus controller. amd developed the models to allow system designers to perform analog simulations of AMD-645 peripheral bus controller signals that interface with the rest of the system. analog simulations are used to determine a signals time of flight from source to destination and to ensure that the systems signal quality requirements are met. signal quality measurements include overshoot, undershoot, slope reversal, and ringing.
10-2 ibis models AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information 10.1 i/o buffer model amd provides models of the AMD-645 peripheral bus controller i/o buffers for system designers to use in board-level simulations. these i/o buffer models conform to the i/o buffer information specification (ibis), version 2.1 . each i/o model contains voltage versus current (v/i) and voltage versus time (v/t) data tables for accurate modeling of i/o buffer behavior. the following list summarizes the properties of each i/o buffer model: n all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. n the pullup, pulldown, power clamp, and ground clamp device v/i tables contain enough data points to accurately represent the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-645 peripheral bus controller for those simulators that yield more accurate results based on this wider range. n rising and falling ramp rates are specified. n the min/typ/max v cc3 operating range is specified as 3.135 v, 3.3 v, and 3.465 v, respectively. n v il = 0.8 v, v ih = 2.0 v, and v meas = 1.5 v. n the r/l/c of the package is modeled. n the capacitance of the silicon die is modeled. n the model assumes 0 capacitance, resistance, inductance, and voltage in the test load.
ibis models 10-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 10.2 i/o model application note for the AMD-645 peripheral bus controller i/o buffer ibis models and their application, refer to the AMD-645 peripheral bus controller i/o model (ibis) application note , order# 21340. the model is available at http://www.amd.com 10.3 i/o buffer ac and dc characteristics refer to section 9 for the AMD-645 peripheral bus controller ac timing specifications. refer to section 8 for the AMD-645 peripheral bus controller dc specifications. 10.4 references ease system simulation with ibis device models by syed huq, electronics design , dec 2, 1996 ibis 2.1 specification at http://vhdl.org/ ibis forum i/o buffer modeling cook book
10-4 ibis models AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information
pin designations 11-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 11 pin designations 11.1 pin designation table the 208 pins of the AMD-645 peripheral bus controller are listed in the following tables, grouped according to their functions. table 11-1. functional grouping eide interface usb interface keyboard interface internal rtc pin no. pin name pin no. pin name pin no. pin name pin no. pin name 50 51 54 55 49 89 56 45 46 47 48 diora# hdmardya/ hstrobea diowa/ stopa diorb/ hdamrdyb/ hstrobeb diowb/ stopb drdya/ddmardy a/ dstrobea drdyb/ ddmardyb dstrobeb soe ddrqa ddrqb ddacka ddackb 95 96 97 98 99 usbdata0+ usbdata0- usbdata1+ usbdata1- usbclk 108 109 110 111 147 106 kbck/ka20g kbdt/kbrc msck/irq1 msdt/irq12 a20m keylock/mirq1 104 105 102 rtcx1/irq8# rtcx2/rtccs# vbat
11-2 pin designations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information table 11-1. functional grouping (continued) cpu interface reset & clock pci bus interface isa bus control pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 142 145 146 143 148 149 141 139 cpurst intr nmi init stpclk# smi# ferr# igenn# 138 3 4 14 6 pwrgd pcirst# rstdrv bclk osc 2 181 204 203 202 201 200 199 196 195 192 191 190 189 187 186 185 183 17 2 170 169 168 167 165 164 163 161 160 159 158 155 154 153 152 194 182 17 3 162 180 17 9 176 17 8 174 175 193 1 207 206 205 151 150 pclk frame ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be3# c/be2# c/be1# c/be0# irdy# trdy# stop# devsel# par serr# idsel pirqa# pirqb# pirqc# pirqd# preq# pgnt# 20 21 22 23 24 25 27 28 36 37 38 40 41 42 43 44 19 63 64 65 66 67 69 70 86 85 83 82 81 80 78 77 62 12 11 123 124 10 9 35 125 76 sa15/dd15 sa14/dd14 sa13/dd13 sa12/dd12 sa11/dd11 sa10/dd10 sa9/dd9 sa8/dd8 sa7/dd7 sa6/dd6 sa5/dd5 sa4/dd4 sa3/dd3 sa2/dd2 sa1/dd1 sa0/dd0 sa16 la23/dcs3b# la22/dcs1b# la21/dcs3a# la20/dcs1a# la19/da2 la18/da1 la17da0 sd15/ gpi15/gpo15 sd14/ gpi14/gpo14 sd13/ gpi13/gpo13 sd12/ gpi12/gpo12 sd11/ gpi11/gpo11 sd10/ gpi10/gpo10 sd9/ gpi9/gpo9 sd8/ gpi8/gpo8 sbhe# ior# iow# memr# memw# smemr# smemw# bale iocs16# memcs16# 5 8 29 15 32 128 129 127 126 61 71 72 73 74 75 132 130 57 30 7 16 59 133 131 58 31 33 18 60 134 iochck# iochrdy refresh# aen tc irq15 irq14 irq11 irq10 irq9 irq7 irq6 irq5 irq4 irq3 drq7 drq6 drq5 drq3 drq2 drq1 drq0 dack7 dack6 dack5 dack3 dack2 dack1 dack0 spkr
pin designations 11-3 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 11.2 pin diagram figure 11-1 shows the pin arrangement of the AMD-645 peripheral bus controller. table 11-1. functional grouping (continued) onboard plug-n-play xd interface power & ground power management/general purpose i/o pin no. pin name pin no. pin name pin no. pin name pin no. pin name 90 106 137 mdrq0/apiccs# mirq1/keylock mirq2/master# 122 121 119 118 117 116 114 113 112 135 xd7/extsmi7#/ gpi7/gpo7 xd6/extsmi6#/gpi6/ gpo6 xd5/extsmi5#/gpi5/ gpo5 xd4/extsmi4#/gpi4/ gpo4 xd3/extsmi3#/gpi3/ gpo3 xd2/extsmi2#/gpi2/ gpo2 xd1/extsmi1#/gpi1/ gpo1 xd0/extsmi0#/ gpi0/gpo0 xdir romcs#/kbcs# 17 34 53 79 115 103 144 157 171 184 198 100 101 13 26 39 52 68 84 120 140 156 166 177 188 197 208 vdd5 vdd5 vdd5 vdd5 vdd5 vdd-5vsb vdd3 vdd_pci vdd_pci vdd_pci vdd_pci avdd agnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 91 107 93 94 87 88 92 136 pwrbtn# pwron ri gpio0/extsmi0 gpio11/extsmi1 i2cd1 gpio12/extsmi2 i2cd2 gpio13/extsmi3 gpi_re# gpio14/extsmi4 gpo_we#
11-4 pin designations AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 11-1. AMD-645 peripheral bus controller pin diagram v dd -pci rtcx1 ad4 v dd -5vsb ad5 vbat ad6 agnd ad7 av dd c/be0# usbclk ad8 usbdata1- ad9 usbdata1+ ad10 usbdata0- gnd usbdata0+ ad11 gpio0 ad12 ri# ad13 gpio3 ad14 pwrbtn# v dd -pci apiccs# ad15 drdyb# c/be1# gpio2 par gpio1 serr# sd15 stop# sd14 gnd gnd devsel# sd13 trdy# sd12 irdy# sd11 frame# sd10 c/be2# v dd 5 ad16 sd9 v dd -pci sd8 ad17 memcs16# ad18 irq3 ad19 irq4 gnd irq5 ad20 irq6 ad21 irq7 ad22 la17/da0 ad23 la18/da1 idsel gnd c/be3# la19/da2 ad24 la20/dcs1a# ad25 la21/dcs3a# gnd la22/dcs1b# v dd -pci la23/dcs3b# ad26 sbhe# ad27 irq9 ad28 dack0# ad29 drq0 ad30 dack5# ad31 drq5 pirqd# soe# pirqc# diowb# pirqb# diorb# gnd v dd 5 gnd ad3 ad2 ad1 ad0 preq# pgnt# smi# stpclk# a20m nmi intr v dd 3 init cpurst ferr# gnd ignne# pwrgd master# (mirq2) gpio4 (extsmi4#) romcs# (kbcs#) spkr (strap) dack7# drq7 dack6# drq6# irq14 irq15 irq11 irq10 iocs16# memw# memr# xd7 (strap) (extsmi7#) xd6 (strap) (extsmi6#) gnd xd5 (strap) (extsmi5#) xd4 (strap) (extsmi4#) xd3 (strap) (extsmi3#) xd2 (strap) v dd 5 xd1 (strap) xd0 (strap) xdir msdt (irq12) msck (ka20g) kbdt (kbrc#) kbck (irq1) pwron keylock (mirq1) rtcx2 (rtccs#) pirqa# pciclk pcirst# rstdrv iochck# osc drq2 iochrdy smemw# smemr# iow# ior# gnd bclk aen drq1 v dd 5 dack1# sa16 dd15/sa15 dd14/sa14 dd13/sa13 dd12/sa12 dd11/sa11 dd10/sa10 gnd dd9/sa9 dd8/sa8 refresh# drq3 dack3# tc dack2# v dd 5 bale dd7/sa7 dd6/sa6 dd5/sa5 gnd dd4/sa4 dd3/sa3 dd2/sa2 dd1/sa1 dd0/sa0 ddrqa ddrqb ddacla# ddaclb# drdya# diora# diowa# gnd 157 158 io 159 io 160 io 161 io 162 i o 163 i o 164 io 165 i o 166 167 io 168 io 169 io 170 io 171 172 i o 173 i o 174 i o 175 i 176 io 177 178 io 179 io 180 io 181 io 182 i o 183 i o 184 185 i o 186 io 187 io 188 189 io 190 io 191 io 192 i o 193 i 194 io 195 i o 196 io 197 198 199 io 200 io 201 io 202 io 203 io 204 io 205 i 206 i 207 i 208 i (irq8#) i 104 103 i 102 101 100 i 99 io 98 io 97 io 96 io 95 (extsmi0#) o 94 i 93 (gpi_re#) (extsmi3#) io 92 i 91 (mirq0) io 90 i 89 (data) (i2cd2) (extsmi2#) io 88 (clock) (i2cd1) (extsmi1#) io 87 (gpi15) (gpo15) io 86 (gpi14) (gpo14) io 85 84 (gpi13) (gpo13) io 83 (gpi12) (gpo12) io 82 (gpi11) (gpo11) io 81 (gpi10) (gpo10) io 80 79 (gpi9) (gpo0) io 78 (gpi8) (gpo8) io 77 i 76 i 75 i 74 i 73 i 72 i 71 io 70 io 69 68 io 67 io 66 io 65 io 64 io 63 io 62 i 61 o 60 i 59 o 58 i 57 o 56 o 55 o 54 53 1 i 2 i 3 0 4 0 5 i 6 i 7 i 8 i 9 o 10 o 11 i o 12 i o 13 14 o 15 o 16 i 17 18 o 19 i o 20 io 21 i o 22 io 23 io 24 io 25 io 26 27 io 28 io 29 io 30 i 31 o 32 o 33 o 34 35 o 36 io 37 io 38 io 39 40 io 41 i o 42 io 43 io 44 io 45 i 46 i 47 o 48 o 49 i 50 o 51 0 52 156 io 155 io 154 io 153 io 152 o 151 i 150 o 149 o 148 o 147 o 146 o 145 144 o 143 o 142 o 141 140 o 139 i 138 i 137 (gpo_we) io136 o 135 io 134 o 133 i 132 o 131 i 130 i 129 i 128 i 127 i 126 i 125 io 124 io 123 (gpi7) gpo7) io 122 (gpi6) gpo6) io 121 120 (gpi5) gpo5) i o 119 (gpi4) gpo4) i o 118 (gpi3) gpo3) io 117 (gpi2) gpo2) i o 116 115 (gpi1) gpo1) i o 114 (gpi0) gpo0) i o 113 o 112 io 111 io 110 io 109 io 108 o 107 i 106 o 105 AMD-645 peripheral bus controller
package specifications 12-1 21095b/0june 1997 AMD-645 peripheral bus controller data sheet preliminary information 12 package specifications the AMD-645 peripheral bus controller is available as a 208- pin plastic quad flat pack (pqfp). the thermal specifications are as follows: q ja = 37 o c/w q jc = 4.7 o c/w figure 12-1 is a drawing of the 208-pin pqfp.
12-2 package specifications AMD-645 peripheral bus controller data sheet 21095b/0june 1997 preliminary information figure 12-1. 208-pin plastic quad flat pack outline drawing m 0.08 27.2 + 156 157 0.85typ 30.6+/-0.2 27.2+/-0.4 105 104 53 1 0.85typ 208 0.5 0.2+/-0.1 52 3.35+/-0.4 4. 6 0.1 0.55 +0.3 -0.2 29.6+/-0.4 0.15 +0.1 -0.05 0~10 o 0.5+/-0.2

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